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* Allow vectorization of few missed llvm intrinsic calls in BBVectorizor by ↵Karthik Bhat2014-04-241-1/+218
| | | | | | handling them in isVectorizableIntrinsic function. llvm-svn: 207085
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-243-0/+103
| | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. llvm-svn: 207080
* [InstCombine][x86] Constant fold psll intrinsics.Michael J. Spencer2014-04-241-0/+110
| | | | | | | | | | | | This excludes avx512 as I don't have hardware to verify. It excludes _dq variants because they are represented in the IR as <{2,4} x i64> when it's actually a byte shift of the entire i{128,265}. This also excludes _dq_bs as they aren't at all supported by the backend. There are also no corresponding instructions in the ISA. I have no idea why they exist... llvm-svn: 207058
* Optimize some special cases for SSE4a insertqiFilipe Cabecinhas2014-04-241-0/+97
| | | | | | | | | | | | | | | | | | | | Summary: Since the upper 64 bits of the destination register are undefined when performing this operation, we can substitute it and let the optimizer figure out that only a copy is needed. Also added range merging, if an instruction copies a range that can be merged with a previous copied range. Added test cases for both optimizations. Reviewers: grosbach, nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3357 llvm-svn: 207055
* Handle addrspacecast when looking at memcpys from globalsMatt Arsenault2014-04-241-4/+63
| | | | llvm-svn: 207054
* MC: disable test on thumbv7-windowsSaleem Abdulrasool2014-04-231-1/+0
| | | | | | | This is dependent on changes that are not fully ready to be merged yet (WoA object file emission). The test can be re-enabled for that target later. llvm-svn: 207038
* llvm-cov: Add support for gcov's --long-file-names optionJustin Bogner2014-04-233-0/+26
| | | | | | | | GCOV provides an option to prepend output file names with the source file name, to disambiguate between covered data that's included from multiple sources. Add a flag to llvm-cov that does the same. llvm-svn: 207035
* MC: move test from Generic to COFFSaleem Abdulrasool2014-04-231-0/+0
| | | | | | This is a COFF specific test, move it to COFF to fix the Hexagon buildbots. llvm-svn: 207030
* MC: move ARM64 test from AArch64 directorySaleem Abdulrasool2014-04-231-0/+0
| | | | | | | The test was changed from aarch64 to arm64 but not moved. The test would fail if the backend was not built. llvm-svn: 207029
* MC: honour IMAGE_SCN_CNT_INITIALIZED_DATASaleem Abdulrasool2014-04-2312-27/+35
| | | | | | | Emit the flag to indicate to the assembler that a section contains data if there is pre-populated data present. llvm-svn: 207028
* [ARM64] Fix the information we give to the peephole optimizer for comparison.Quentin Colombet2014-04-231-0/+31
| | | | | | | | | ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
* R600: Add a test that used to be broken that I forgot to addMatt Arsenault2014-04-231-0/+29
| | | | llvm-svn: 207017
* Convert test to FileCheckMatt Arsenault2014-04-231-1/+5
| | | | llvm-svn: 207015
* Mark llvm/test/BugPoint/compile-custom.ll as XFAIL:vg_leak.NAKAMURA Takumi2014-04-231-0/+2
| | | | llvm-svn: 206989
* Create MCTargetOptions.Evgeniy Stepanov2014-04-234-23/+23
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* [LV] Statistics numbers for LoopVectorize introduced: a number of analyzed ↵Alexander Musman2014-04-231-0/+66
| | | | | | | | | | | loops & a number of vectorized loops. Use -stats to see how many loops were analyzed for possible vectorization and how many of them were actually vectorized. Patch by Zinovy Nis Differential Revision: http://reviews.llvm.org/D3438 llvm-svn: 206956
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-231-0/+4
| | | | llvm-svn: 206953
* Integrated assbemler, macros: added 'vararg' argument qualifier support.Stepan Dyatkovskiy2014-04-233-0/+64
| | | | | | Note, currently we have no 'vararg' support for darwin macros. llvm-svn: 206951
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-2318-16/+76
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
* Fix test/CodeGen/arm.llReid Kleckner2014-04-231-4/+4
| | | | | | | The 'CHECK: add' line was occasionally matching against the filename, breaking the subsequent CHECK-NOT. Also use CHECK-LABEL. llvm-svn: 206936
* Follow aliases when determining if a symbol is thumb.Rafael Espindola2014-04-221-1/+11
| | | | | | This fixes pr19484. llvm-svn: 206917
* [Constant Hoisting] Materialize the constant before the cloned cast instruction.Juergen Ributzka2014-04-221-0/+29
| | | | | | | | | | | | In the case where the constant comes from a cloned cast instruction, the materialization code has to go before the cloned cast instruction. This commit fixes the method that finds the materialization insertion point by making it aware of this case. This fixes <rdar://problem/15532441> llvm-svn: 206913
* Fix DataLayout::operator==().Rafael Espindola2014-04-221-1/+1
| | | | | | Patch by Maks Naumov! llvm-svn: 206911
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 llvm-svn: 206906
* R600: Emit error instead of unreachable on function callMatt Arsenault2014-04-221-0/+33
| | | | llvm-svn: 206904
* AVX-512: store and truncstore for i1 valuesElena Demikhovsky2014-04-221-3/+22
| | | | llvm-svn: 206897
* AArch64/ARM64: more testing from AArch64 to ARM64Tim Northover2014-04-225-8/+87
| | | | llvm-svn: 206889
* AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.Tim Northover2014-04-223-7/+7
| | | | llvm-svn: 206888
* AArch64/ARM64: add extra testing from AArch64 to ARM64Tim Northover2014-04-2219-1/+1079
| | | | llvm-svn: 206887
* [AVX512] Implemented integer conversions up/down with masking.Robert Khasanov2014-04-221-96/+1064
| | | | | | Added encoding tests. llvm-svn: 206884
* [asan] Support outline instrumentation for wide types and delete dead code, ↵Kostya Serebryany2014-04-221-1/+6
| | | | | | patch by Yuri Gribov llvm-svn: 206883
* AArch64/ARM64: enable various AArch64 tests on ARM64.Tim Northover2014-04-2213-18/+34
| | | | llvm-svn: 206877
* AArch64/ARM64: add patterns for scalar_to_vector/extract pairsTim Northover2014-04-221-33/+42
| | | | llvm-svn: 206876
* AArch64/ARM64: mark fmul intrinsic as commutative.Tim Northover2014-04-222-1/+125
| | | | | | | This gives DAG patterns matching indexed patterns where either side is an indexed vector. llvm-svn: 206875
* ARM: disable emission of __XYZvfp in soft-float environment.Tim Northover2014-04-221-0/+11
| | | | | | | | | | The point of these calls is to allow Thumb-1 code to make use of the VFP unit to perform its operations. This is not desirable with -msoft-float, since most of the reasons you'd want that apply equally to the runtime library. rdar://problem/13766161 llvm-svn: 206874
* Fix an infinite loop bug in DAG Combine about keeping transfering between ↵Hao Liu2014-04-222-1/+31
| | | | | | ANY_EXTEND and SIGN_EXTEND. llvm-svn: 206873
* [X86] Don't use BZHI for short masks (>=32 bits). Thanks to Ben Kramer for theLang Hames2014-04-221-10/+9
| | | | | | review. llvm-svn: 206869
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-0/+13
| | | | | | Don't know why I didn't just do this in the first place. llvm-svn: 206862
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-221-0/+17
| | | | llvm-svn: 206861
* blockfreq: Skip irreducible backedges inside functionsDuncan P. N. Exon Smith2014-04-221-0/+31
| | | | | | | | | | | | The branch that skips irreducible backedges was only active when propagating mass at the top-level. In particular, when propagating mass through a loop recognized by `LoopInfo` with irreducible control flow inside, irreducible backedges would not be skipped. Not sure where that idea came from, but the result was that mass was lost until after loop exit. Added a testcase that covers this case. llvm-svn: 206860
* [CodeGenPrepare] Use APInt to check the value of the immediate in a andQuentin Colombet2014-04-221-0/+23
| | | | | | | | | | while checking candidate for bit field extract. Otherwise the value may not fit in uint64_t and this will trigger an assertion. This fixes PR19503. llvm-svn: 206834
* Simplify a vpermil* with constant mask.Rafael Espindola2014-04-211-0/+30
| | | | | | | | With a constant mask a vpermil* is just a shufflevector. This patch implements that simplification. This allows us to produce denser code. It should also allow more folding down the line. llvm-svn: 206801
* ARM64: Improve diagnostics for malformed reg+reg addressing mode.Jim Grosbach2014-04-211-0/+12
| | | | | | | Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
* Handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode.Rafael Espindola2014-04-211-0/+5
| | | | | | | | | With this MC is able to handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode, which is needed for medium and large code models. This fixes pr19470. llvm-svn: 206793
* Fix PR7272 in -tailcallelim instead of the inlinerReid Kleckner2014-04-212-4/+25
| | | | | | | | | | | | | | | | The -tailcallelim pass should be checking if byval or inalloca args can be captured before marking calls as tail calls. This was the real root cause of PR7272. With a better fix in place, revert the inliner change from r105255. The test case it introduced still passes and has been moved to test/Transforms/Inline/byval-tail-call.ll. Reviewers: chandlerc Differential Revision: http://reviews.llvm.org/D3403 llvm-svn: 206789
* ARM64: Combine shifts and uses from different basic block to bit-extract ↵Yi Jiang2014-04-211-0/+73
| | | | | | instruction llvm-svn: 206774
* Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"Duncan P. N. Exon Smith2014-04-217-28/+548
| | | | | | | | | This reverts commit r206707, reapplying r206704. The preceding commit to CalcSpillWeights should have sorted out the failing buildbots. <rdar://problem/14292693> llvm-svn: 206766
* Fix the test: DCE optimized away everything.Eli Bendersky2014-04-211-9/+9
| | | | | | | | Use volatile store to protect the generated PTX from DCE. Patch by Jingyue Wu. llvm-svn: 206763
* Reapply r206732. This time without optimization of branches.Michael Zolotukhin2014-04-214-0/+461
| | | | llvm-svn: 206749
* [asan] add llvm-ish test for memset/etc instrumentationKostya Serebryany2014-04-211-0/+17
| | | | llvm-svn: 206747
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