| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 55605
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
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combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.
llvm-svn: 55579
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Based on patch by Giorgos Korfiatis.
llvm-svn: 55570
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the implicit defs onto the remat'ed instruction.
llvm-svn: 55564
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shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
llvm-svn: 55558
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llvm-svn: 55556
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(safely this time).
llvm-svn: 55553
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llvm-svn: 55550
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llvm-svn: 55540
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nameless values, such as:
%3 = add i32 4, 2
This fixes the first half of PR2480
llvm-svn: 55539
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llvm-svn: 55521
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when the compare value has a NaN
llvm-svn: 55499
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its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
llvm-svn: 55498
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Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
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Re-materialize the src to replace the copy.
llvm-svn: 55467
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Feel free to fix a better way!
llvm-svn: 55456
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verifier. See PR2711 for details.
llvm-svn: 55414
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llvm-svn: 55401
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the cast operation.
llvm-svn: 55374
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assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
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done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
llvm-svn: 55338
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and use them to support
bitcast of constants in fast isel.
llvm-svn: 55325
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llvm-svn: 55320
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llvm-svn: 55300
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llvm-svn: 55296
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/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
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into the call node.
llvm-svn: 55292
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llvm-svn: 55239
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integer, PR2318.
llvm-svn: 55228
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indices that start with an array subscript. x->field[10000] is just
as bad as (*X)[14][10000].
llvm-svn: 55226
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These just test that they go through the BE.
llvm-svn: 55208
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llvm-svn: 55206
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
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llvm-svn: 55151
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llvm-svn: 55145
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llvm-svn: 55141
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1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
llvm-svn: 55139
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has MOV64ri32 and no plain MOV64ri.
llvm-svn: 55126
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intptr_t type in this case. FastISel can now select simple
getelementptr instructions.
llvm-svn: 55125
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slowdown in bzip2.
llvm-svn: 55113
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llvm-svn: 55099
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llvm-svn: 55030
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llvm-svn: 55025
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llvm-svn: 55021
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llvm-svn: 55020
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was already present, but not hooked up to anything.
llvm-svn: 55018
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demonstrate the extent of its capabilities. Note that it
only attempts to operate on one of the blocks in this
testcase.
llvm-svn: 55016
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builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
llvm-svn: 54999
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llvm-svn: 54929
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