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* Convert more Neon tests to FileCheck.Bob Wilson2009-08-052-10/+42
| | | | llvm-svn: 78261
* Adjust test for llvm-gcc checkin 78249.Dale Johannesen2009-08-051-2/+2
| | | | llvm-svn: 78251
* Test for llvm-gcc checkin 78223.Dale Johannesen2009-08-051-0/+5
| | | | llvm-svn: 78229
* Missed pieces for ARM HardFP ABI.Anton Korobeynikov2009-08-051-0/+13
| | | | | | Patch by Sandeep Patel! llvm-svn: 78225
* Enable the new no-SP register classes by default. This is to addressDan Gohman2009-08-053-3/+3
| | | | | | | PR4572. A few tests have some minor code regressions due to different coalescing. llvm-svn: 78217
* Add testcases for reg-mem arithemtics added recentlyAnton Korobeynikov2009-08-051-0/+133
| | | | llvm-svn: 78214
* Convert bswap test to filecheck, add more test entries & convert stuff to ↵Anton Korobeynikov2009-08-051-6/+31
| | | | | | filecheck llvm-svn: 78212
* Fix a bug in the PIC16 backend.Dan Gohman2009-08-051-1/+0
| | | | llvm-svn: 78211
* Change these tests to use function attributes rather than special llcDan Gohman2009-08-052-9/+21
| | | | | | command-line options. llvm-svn: 78204
* checking in broken testcases is not such a good idea.Chris Lattner2009-08-051-0/+1
| | | | llvm-svn: 78201
* Quite a few tests crashed in llc after 78142. This is just one of them. I ↵Sanjiv Gupta2009-08-051-0/+10
| | | | | | hope to add a few more. llvm-svn: 78198
* Disable stack coloring with register for now. It's not able to set kill markers.Evan Cheng2009-08-051-0/+508
| | | | llvm-svn: 78179
* Another nasty coalescer bug (is there another kind):Evan Cheng2009-08-051-0/+153
| | | | | | | | | | | | | | | | After coalescing reg1027's def and kill are both at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814) bb5: 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def> 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill> Do not remove the kill marker on t2LDRi12. llvm-svn: 78178
* Revert changes accidentally committed along with r78163.Dan Gohman2009-08-052-2/+2
| | | | llvm-svn: 78165
* Teach X86FastISel how to handle CCValAssign::BCvt, which is used forDan Gohman2009-08-053-2/+21
| | | | | | MMX arguments. This fixes PR4684. llvm-svn: 78163
* ZIV tester for LDA.Andreas Bolka2009-08-052-3/+3
| | | | llvm-svn: 78157
* Fix LDA testcases.Andreas Bolka2009-08-051-4/+4
| | | | llvm-svn: 78153
* Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.Evan Cheng2009-08-051-3/+0
| | | | llvm-svn: 78151
* One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.Evan Cheng2009-08-051-0/+54
| | | | llvm-svn: 78145
* One more place where subreg lowering forgot to transfer undefness.Evan Cheng2009-08-051-0/+42
| | | | llvm-svn: 78144
* Major calling convention code refactoring.Dan Gohman2009-08-051-8/+11
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* If the insert_subreg source is <undef>, insert an implicit_def instead of a ↵Evan Cheng2009-08-051-0/+34
| | | | | | copy. llvm-svn: 78141
* Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.Evan Cheng2009-08-042-2/+2
| | | | llvm-svn: 78126
* Fix test.Evan Cheng2009-08-041-1/+1
| | | | llvm-svn: 78113
* Convert more Neon tests to use FileCheck.Bob Wilson2009-08-043-16/+31
| | | | llvm-svn: 78111
* Convert a few Neon tests to use FileCheck.Bob Wilson2009-08-043-20/+71
| | | | llvm-svn: 78108
* Clean up the handling of two-address operands in RegScavenger.Jakob Stoklund Olesen2009-08-041-0/+33
| | | | | | This fixes PR4528. llvm-svn: 78107
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-0/+40
| | | | llvm-svn: 78104
* Add NEON single-precision FP support for fabs and fneg.David Goodwin2009-08-042-0/+36
| | | | llvm-svn: 78101
* LowerSubregsInstructionPass::LowerExtract should not extend the live range ↵Jakob Stoklund Olesen2009-08-042-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of registers. When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the kill flag to the place where the sub-register is killed. This can accidentally overlap with the use of a sibling sub-register, and we have trouble. In the test case we have this code: Live Ins: %R0 %R1 %R2 %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0] %R1L<def> = EXTRACT_SUBREG %R1<kill>, 1 %R0L<def> = EXTRACT_SUBREG %R0<kill>, 1 %R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def> subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 subreg: eliminated! subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def> The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H: *** Bad machine code: Redefining a live physical register *** - function: f - basic block: 0x18358c0 (#0) - instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0] Register R2H was defined but already live. The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating it completely: subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill> Note that these IMPLICIT_DEF instructions survive to the asm output. It is necessary to fix the stack-color-with-reg test case because of that. llvm-svn: 78093
* In thumb mode, r7 is used as frame register. This fixes pr4681.Evan Cheng2009-08-041-0/+29
| | | | llvm-svn: 78086
* Match common pattern for FNMAC. Add NEON SP support.David Goodwin2009-08-041-1/+0
| | | | llvm-svn: 78085
* Improve tests.David Goodwin2009-08-042-8/+23
| | | | llvm-svn: 78083
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-049-0/+99
| | | | | | to enable. Added patterns for some binary FP operations. llvm-svn: 78081
* Fix PR4528. This scavenger assertion is too strict. The two-address value isEvan Cheng2009-08-041-0/+25
| | | | | | | | | killed by another operand. There is probably a better fix. Either 1) scavenger can look at other operands, or 2) livevariables can be smarter about kill markers. Patches welcome. llvm-svn: 78072
* enhance codegen to put 16-bit character strings into the Chris Lattner2009-08-041-2/+2
| | | | | | __TEXT,__ustring section on darwin. llvm-svn: 78068
* Add support emiting for 2/4 byte mergable strings to the ".rodata.str*"Chris Lattner2009-08-041-0/+36
| | | | | | section on ELF targets. llvm-svn: 78066
* Use separate ValueList for metadata.Devang Patel2009-08-042-0/+93
| | | | | | This fixes PR4666. llvm-svn: 78056
* Revert recent bitcode writer patches.Devang Patel2009-08-041-5/+0
| | | | llvm-svn: 78053
* llvm-gcc checks the static asm variable is valid in ↵Bill Wendling2009-08-041-0/+4
| | | | | | ValidateRegisterVariable. Make this work for PPC. llvm-svn: 78051
* Fixed now.Bill Wendling2009-08-041-2/+0
| | | | llvm-svn: 78042
* Add test for PR4678Rafael Espindola2009-08-041-0/+4
| | | | llvm-svn: 78040
* XFAIL for the moment.Bill Wendling2009-08-041-0/+2
| | | | llvm-svn: 78038
* Constants and Metadata share ValueList. This means they must be emitted ↵Devang Patel2009-08-041-0/+5
| | | | | | interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync. llvm-svn: 78033
* Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. ↵Evan Cheng2009-08-041-1/+19
| | | | | | This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. llvm-svn: 78030
* Add -disable-output. Thanks Bill!Dan Gohman2009-08-031-1/+1
| | | | llvm-svn: 78009
* Add a new Constant::getIntegerValue helper function, and convert aDan Gohman2009-08-031-0/+84
| | | | | | | few places in InstCombine to use it, to fix problems handling pointer types. This fixes the recent llvm-gcc bootstrap error. llvm-svn: 78005
* Lower CONCAT_VECTOR during legalization instead of matching it during isel.Bob Wilson2009-08-031-0/+36
| | | | | | Add a testcase. llvm-svn: 77992
* Fix Bug 4657: register scavenger asserts with subreg loweringJakob Stoklund Olesen2009-08-031-0/+29
| | | | | | | | | | | | | | | When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG instriction because it is an identity copy, make sure that the same registers are alive before and after the elimination. When the super-register is marked <undef> this requires inserting an IMPLICIT_DEF instruction to make sure the super register is live. Fix a related bug where a kill flag on the inserted sub-register was not transferred properly. Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid. llvm-svn: 77989
* Fix a coaelescer bug. If a copy val# is extended to eliminate a ↵Evan Cheng2009-08-031-0/+46
| | | | | | non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. llvm-svn: 77967
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