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* Unbreak Win64 CC. Step one: honour register save area, fix some alignment ↵Anton Korobeynikov2009-08-032-4/+4
| | | | | | and provide a different set of call-clobberred registers. llvm-svn: 77962
* Use movd instead of movqRafael Espindola2009-08-031-1/+1
| | | | llvm-svn: 77956
* Pass target triple string in to TargetMachine constructor.Daniel Dunbar2009-08-033-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This is not just a matter of passing in the target triple from the module; currently backends are making decisions based on the build and host architecture. The goal is to migrate to making these decisions based off of the triple (in conjunction with the feature string). Thus most clients pass in the target triple, or the host triple if that is empty. This has one important change in the way behavior of the JIT and llc. For the JIT, it was previously selecting the Target based on the host (naturally), but it was setting the target machine features based on the triple from the module. Now it is setting the target machine features based on the triple of the host. For LLC, -march was previously only used to select the target, the target machine features were initialized from the module's triple (which may have been empty). Now the target triple is taken from the module, or the host's triple is used if that is empty. Then the triple is adjusted to match -march. The take away is that -march for llc is now used in conjunction with the host triple to initialize the subtarget. If users want more deterministic behavior from llc, they should use -mtriple, or set the triple in the input module. llvm-svn: 77946
* Use movq to move 64 bits in and out of mmx registers.Rafael Espindola2009-08-032-1/+11
| | | | | | Fixes PR4669 llvm-svn: 77940
* Use the i12 variant of load / store opcodes if offset is zero. Now we pass ↵Evan Cheng2009-08-031-0/+85
| | | | | | all of multisource as well. llvm-svn: 77939
* Expand LDA testcases.Andreas Bolka2009-08-022-11/+62
| | | | llvm-svn: 77926
* Add extra SEXT pattern.Richard Osborne2009-08-021-0/+32
| | | | llvm-svn: 77920
* Remove unneeded intrinsics from Blackfin backend.Jakob Stoklund Olesen2009-08-021-13/+0
| | | | | | | | | | __builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end. __builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load. We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds. llvm-svn: 77917
* Fix issue in regscavenger when scavenging a callee-saved register that has ↵Jakob Stoklund Olesen2009-08-021-3/+3
| | | | | | not been spilled. llvm-svn: 77912
* Never add a kill flag to a constrained physical register in a two-addr ↵Jakob Stoklund Olesen2009-08-022-6/+0
| | | | | | instruction. llvm-svn: 77906
* Scavenger asserts.Jakob Stoklund Olesen2009-08-021-3/+0
| | | | | | | Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier. Allow redefinition of a sub-register of a live register. llvm-svn: 77904
* Add some basic blackfin intrinsics.Jakob Stoklund Olesen2009-08-022-0/+29
| | | | llvm-svn: 77903
* Inline assembly support for Blackfin.Jakob Stoklund Olesen2009-08-021-0/+38
| | | | | | We use the same constraints as GCC, including those that are slightly insane for inline assembler. llvm-svn: 77899
* Analog Devices Blackfin back-end.Jakob Stoklund Olesen2009-08-0247-0/+1238
| | | | | | | | | | | | | | Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
* Test both darwin and linux.Evan Cheng2009-08-021-5/+12
| | | | llvm-svn: 77852
* switch to filecheck formatChris Lattner2009-08-021-12/+12
| | | | llvm-svn: 77841
* fix a problem Eli noticed where we would compile the attached ptrtointChris Lattner2009-08-011-0/+8
| | | | | | | | | | | | | | | to: .quad X even on a 32-bit system, where X is not 64-bits. There isn't much that we can do here, so we just print: .quad ((X) & 4294967295) instead. llvm-svn: 77818
* Add nounwind to this test.Dan Gohman2009-08-011-1/+1
| | | | llvm-svn: 77792
* Hack to make this test work on platforms which aren't Macs. Fixing this Eli Friedman2009-08-011-1/+1
| | | | | | | | | | myself because I'm getting tired of seeing the red buildbots, which have been red since 5:30PM PDT last night. Proposed supplement to developer policy: committers should make sure to be around to watch for buildbot failures after committing. llvm-svn: 77785
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-1/+1
| | | | llvm-svn: 77781
* Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan!Daniel Dunbar2009-08-011-4/+9
| | | | llvm-svn: 77767
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-011-0/+35
| | | | | | alias with predicate. llvm-svn: 77764
* llvm-mc: More quoted identifier support.Daniel Dunbar2009-08-011-0/+25
| | | | llvm-svn: 77761
* Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the sameEvan Cheng2009-08-012-1/+21
| | | | | | | | | instructions for calls since BL and BLX are always 32-bit long and BX is always 16-bit long. Also, we should be using BLX to call external function stubs. llvm-svn: 77756
* llvm-mc: Add -triple, and fix some typosDaniel Dunbar2009-07-312-3/+3
| | | | llvm-svn: 77750
* llvm-mc: Fix .s output to quote section & symbol names when necessary.Daniel Dunbar2009-07-312-8/+8
| | | | llvm-svn: 77749
* llvm-mc: A few more parsing / match tweaks.Daniel Dunbar2009-07-311-0/+27
| | | | | | | | | | | | | | - Operands which are just a label should be parsed as immediates, not memory operands (from the assembler perspective). - Match a few more flavors of immediates. - Distinguish match functions for memory operands which don't take a segment register. - We match the .s for "hello world" now! llvm-svn: 77745
* Simplify operand padding by keying off tabs in the asm stream. IfDavid Greene2009-07-315-13/+13
| | | | | | | | | | | | padding is disabled, tabs get replaced by spaces except in the case of the first operand, where the tab is output to line up the operands after the mnemonics. Add some better comments and eliminate redundant code. Fix some testcases to not assume tabs. llvm-svn: 77740
* llvm-mc: Support quoted identifiers.Daniel Dunbar2009-07-311-0/+26
| | | | | | | | | - Uses MCAsmToken::getIdentifier which returns the (sub)string representing the meaningfull contents a string or identifier token. - Directives aren't done yet. llvm-svn: 77739
* llvm-mc/X86: Sketch match functions for immediates and memory operands.Daniel Dunbar2009-07-311-2/+14
| | | | | | | Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
* PR4662: Fix a crash introduced by the recent LLVMContext changes.Eli Friedman2009-07-311-0/+14
| | | | llvm-svn: 77716
* switch off of 'Section' onto MCSection. We're not properly usingChris Lattner2009-07-311-2/+1
| | | | | | MCSection subclasses yet, but this is a step in the right direction. llvm-svn: 77708
* Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .alignEvan Cheng2009-07-311-0/+1
| | | | | | | | to ensure the instruction that follows a TBB (when the number of table entries is odd) is 2-byte aligned. Patch by Sandeep Patel. llvm-svn: 77705
* fix PR4650: we only track sizes for certain objects, so only put somethingChris Lattner2009-07-311-0/+17
| | | | | | | | into the mergable section if it is one of our special cases. This could obviously be improved, but this is the minimal fix and restores us to the previous behavior. llvm-svn: 77679
* Add this test back, the check pattern was too strict.Daniel Dunbar2009-07-311-0/+7
| | | | llvm-svn: 77662
* Remove this test while I figure out why it is failing.Daniel Dunbar2009-07-311-5/+0
| | | | llvm-svn: 77659
* llvm-mc: Match a few X86 instructions.Daniel Dunbar2009-07-312-1/+6
| | | | | | | | | | | - This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. llvm-svn: 77657
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-301-0/+193
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Do not use abbrev while writing NamedMDNode name.Devang Patel2009-07-301-0/+7
| | | | llvm-svn: 77637
* Darwin assembler now recognizes "orn", so remove workaround.David Goodwin2009-07-302-2/+0
| | | | llvm-svn: 77627
* Darwin assembler now supports "rrx", so remove workaround.David Goodwin2009-07-301-2/+2
| | | | llvm-svn: 77625
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-1/+1
| | | | llvm-svn: 77622
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-302-1/+221
| | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582
* Add a new register class to describe operands that can't be SP,Dan Gohman2009-07-301-0/+36
| | | | | | | due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
* tbb / tbh instructions only branch forward, not backwards.Evan Cheng2009-07-292-0/+124
| | | | llvm-svn: 77522
* Add VFP3 D registers to the DPR register class.Evan Cheng2009-07-291-0/+108
| | | | llvm-svn: 77521
* Read and write NamedMDNode.Devang Patel2009-07-291-0/+6
| | | | llvm-svn: 77517
* Fix PR4645 which was fallout from the fix for PR4641.Daniel Dunbar2009-07-291-0/+24
| | | | | | - Call RAUW to delete all instructions (this is a patch from Nick Lewycky). llvm-svn: 77512
* xfail for now.Evan Cheng2009-07-291-0/+1
| | | | llvm-svn: 77478
* Change Neon VLDn intrinsics to return multiple values instead of reallyBob Wilson2009-07-292-40/+40
| | | | | | | wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. llvm-svn: 77468
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