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* Enable using vdup for vector constants which are splat ofDale Johannesen2010-10-192-41/+4
| | | | | | | integers by default, and remove the controlling flag, now that LICM will hoist such vdup's. 8003375. llvm-svn: 116852
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-194-69/+11
| | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
* Fixing r116753 r116756 r116777Jason W Kim2010-10-1933-584/+619
| | | | | | | | | | | | | | | | | | | The failures in r116753 r116756 were caused by a python issue - Python likes to append 'L' suffix to stringified numbers if the number is larger than a machine int. Unfortunately, this causes a divergence of behavior between 32 and 64 bit python versions. I re-crafted elf-dump/common_dump to take care of these issues by: 1. always printing 0x (makes for easy sed/regex) 2. always print fixed length (exactly 2 + numBits/4 digits long) by mod ((2^numBits) - 1) 3. left-padded with '0' There is a residual common routine that is also used by macho-dump (dataToHex) , so I left the 'section_data' test values alone. llvm-svn: 116823
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-194-11/+69
| | | | | | is", which breaks some nightly tests. llvm-svn: 116816
* GlobalOpt: EvaluateFunction() must not evaluate stores to weak_odr globals.Mikhail Glushenkov2010-10-191-0/+16
| | | | | | Fixes PR8389. llvm-svn: 116812
* Add test case mov.ll for PTX device functionChe-Liang Chiou2010-10-191-0/+13
| | | | llvm-svn: 116806
* Fix PR8300 by remembering to keep the bitcast in all cases.Rafael Espindola2010-10-191-0/+13
| | | | llvm-svn: 116788
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-194-69/+11
| | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781
* Speculatively revert 116753 and 116756 to attempt to fix the bots.Eric Christopher2010-10-1932-582/+582
| | | | llvm-svn: 116777
* Support alignment for NEON vld-lane and vst-lane instructions.Bob Wilson2010-10-192-39/+59
| | | | llvm-svn: 116776
* Added a few tweaks to the Intel Descriptor-table support instructions to allowKevin Enderby2010-10-192-0/+80
| | | | | | | word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . llvm-svn: 116773
* Revert r116220 - thus turning arm fast isel back on by default.Eric Christopher2010-10-181-2/+2
| | | | llvm-svn: 116762
* Get rid of unneeded FormatOutput global variableJason W Kim2010-10-181-50/+48
| | | | llvm-svn: 116756
* Changed elf-dump to output hex format by default.Jason W Kim2010-10-1832-582/+584
| | | | | | Also updated tests. llvm-svn: 116753
* Don't pass the raw invalid pointer used to represent conflictingDan Gohman2010-10-181-0/+28
| | | | | | TBAA information to AliasAnalysis. llvm-svn: 116751
* Add a basic testcase for TBAA-aware LICM.Dan Gohman2010-10-181-0/+33
| | | | llvm-svn: 116745
* Implement R_386_GOT32.Rafael Espindola2010-10-181-1/+10
| | | | llvm-svn: 116744
* Relocate with .bss instead of using the symbol. Matches gas behavior.Rafael Espindola2010-10-181-0/+25
| | | | llvm-svn: 116741
* Run tbaa before basicaa, since that's how it's expected to be used.Dan Gohman2010-10-181-1/+1
| | | | llvm-svn: 116731
* Produce ELF::R_386_GOTPC relocations.Rafael Espindola2010-10-181-0/+7
| | | | llvm-svn: 116728
* Make TypeBasedAliasAnalysis default to doing nothing, with a command-lineDan Gohman2010-10-181-1/+1
| | | | | | option to enable it. llvm-svn: 116722
* Make BasicAliasAnalysis a normal AliasAnalysis implementation whichDan Gohman2010-10-1878-80/+80
| | | | | | | | | | | | does normal initialization and normal chaining. Change the default AliasAnalysis implementation to NoAlias. Update StandardCompileOpts.h and friends to explicitly request BasicAliasAnalysis. Update tests to explicitly request -basicaa. llvm-svn: 116720
* Added a handful of x86-32 instructions that were missing so that llvm-mc wouldKevin Enderby2010-10-182-0/+73
| | | | | | | | | | be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
* Produce a R_386_PLT32 when needed. Moved the default cases of switches to theRafael Espindola2010-10-181-3/+13
| | | | | | start for consistency. llvm-svn: 116715
* Handle GOTOFF correctly on i386.Rafael Espindola2010-10-181-0/+20
| | | | llvm-svn: 116711
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-0/+3
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Add a MCObjectFormat class so that code common to all targets that use aRafael Espindola2010-10-162-0/+28
| | | | | | | | | | | | single object format can be shared. This also adds support for mov zed+(bar-foo), %eax on ELF and COFF targets. llvm-svn: 116675
* Unbreak test on non-COFF targets.Benjamin Kramer2010-10-161-1/+1
| | | | llvm-svn: 116669
* MC-COFF: Add support for default-null weak externals.Michael J. Spencer2010-10-161-0/+51
| | | | llvm-svn: 116666
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+17
| | | | | | if any floating point arguments are passed to an external function. llvm-svn: 116665
* Generalize MemCpyOpt's handling of call slot forwarding to function properly ↵Owen Anderson2010-10-151-0/+25
| | | | | | | | when the call slot forwarding is implemented with a load/store pair rather than a memcpy. llvm-svn: 116637
* llvmc: Add a test for the -c flag.Mikhail Glushenkov2010-10-151-0/+10
| | | | llvm-svn: 116611
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+15
| | | | llvm-svn: 116588
* FileCheckizeJakob Stoklund Olesen2010-10-151-2/+16
| | | | llvm-svn: 116581
* Refactor code a bit and avoid creating unnecessary entries in the stringRafael Espindola2010-10-151-5/+5
| | | | | | map. llvm-svn: 116579
* ARM instructions that are both predicated and set the condition codesBob Wilson2010-10-152-3/+50
| | | | | | | | | | have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! llvm-svn: 116563
* Simplify test file a bit.Jim Grosbach2010-10-141-10/+10
| | | | llvm-svn: 116540
* Add testcase for RRX and ASRS (which effectively tests MOVs, since thoseJim Grosbach2010-10-141-0/+8
| | | | | | are just forms of that instruction). llvm-svn: 116538
* Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudosJim Grosbach2010-10-141-1/+1
| | | | | | | and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
* Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach2010-10-141-1/+1
| | | | | | pseudonym. llvm-svn: 116512
* MOVi16 and MOVT ARM mode encodings.Jim Grosbach2010-10-141-0/+17
| | | | llvm-svn: 116498
* Remove some code duplication.Rafael Espindola2010-10-142-8/+8
| | | | llvm-svn: 116484
* Comments.Mikhail Glushenkov2010-10-142-0/+4
| | | | llvm-svn: 116476
* Add support for vmov.f64/.f32 encoding. There's a bit of a hack going onBill Wendling2010-10-141-0/+16
| | | | | | | | | here. The f32 in FCONSTS is handled as a double instead of a float in the code. So the encoding of the immediate into the instruction isn't exactly in line with the documentation in that regard. But given that we know it's handled as a double, it doesn't cause any harm. llvm-svn: 116471
* Add encoding for 'fmstat'.Bill Wendling2010-10-141-0/+2
| | | | llvm-svn: 116466
* - Add encodings for multiply add/subtract instructions in all their glory.Bill Wendling2010-10-141-0/+94
| | | | | | | - Add missing patterns for some multiply add/subtract instructions. - Add encodings for VMRS and VMSR. llvm-svn: 116464
* fix a bug I introduced, no idea how this didn't repro right.Chris Lattner2010-10-141-2/+1
| | | | llvm-svn: 116462
* hack to unbreak buildbotsChris Lattner2010-10-141-1/+2
| | | | llvm-svn: 116461
* add uadd_ov/usub_ov to apint, consolidate constant foldingChris Lattner2010-10-141-0/+11
| | | | | | | | | logic to use the new APInt methods. Among other things this implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold which comes from "clang -ftrapv", originally brought to my attention from PR8221. llvm-svn: 116457
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+6
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
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