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* Make stackmap machineinstrs clobber the scratch regs too.Andrew Trick2014-03-051-2/+22
| | | | | | | | | | | | | Patchpoints already did this. Doing it for stackmaps is a convenience for the runtime in the event that it needs to scratch register to patch or perform a runtime call thunk. Unlike patchpoints, we just assume the AnyRegCC calling convention. This is the only language and target independent calling convention specific to stackmaps so makes sense. Although the calling convention is not currently used to select the scratch registers. llvm-svn: 202943
* Check for dynamic allocas and inline asm that clobbers sp before buildingHans Wennborg2014-03-052-1/+43
| | | | | | | | | | | | | | | | | | | selection dag (PR19012) In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo to make sure that ESI isn't used as a base pointer register before we choose to emit rep movs (which clobbers esi). The problem is that MachineFrameInfo wouldn't know about dynamic allocas or inline asm that clobbers the stack pointer until SelectionDAGBuilder has encountered them. This patch fixes the problem by checking for such things when building the FunctionLoweringInfo. Differential Revision: http://llvm-reviews.chandlerc.com/D2954 llvm-svn: 202930
* Trivial test commit.Raul E. Silvera2014-03-051-0/+1
| | | | llvm-svn: 202924
* Allow constant folding of fma and fmuladdMatt Arsenault2014-03-051-0/+39
| | | | llvm-svn: 202914
* llvm-objdump: Indent unwind info contents.Rui Ueyama2014-03-041-80/+80
| | | | | | | | | | | Unwind info contents were indented at the same level as function table contents. That's a bit confusing because the unwind info is pointed by function table. In other places we usually increment indentation depth by one when dereferncing a pointer. This patch also removes extraneous newlines between function tables. llvm-svn: 202879
* llvm-objdump: Fix typo in output.Rui Ueyama2014-03-041-4/+4
| | | | llvm-svn: 202875
* [XCore] Fix call of absolute address.Richard Osborne2014-03-041-0/+10
| | | | | | | | | | | | | | | Previously for: tail call void inttoptr (i64 65536 to void ()*)() nounwind We would emit: bl 65536 The immediate operand of the bl instruction is a relative offset so it is wrong to use the absolute address here. llvm-svn: 202860
* [CMake] check-llvm: Include "bugpoint" in dependent list.NAKAMURA Takumi2014-03-041-0/+1
| | | | llvm-svn: 202858
* [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.Daniel Sanders2014-03-041-0/+18
| | | | | | | | | | Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 llvm-svn: 202848
* This patch implements .set mips32r2 directive and sets appropriate feature ↵Vladimir Medic2014-03-041-1/+10
| | | | | | bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
* llvm-objdump: Print x64 unwind info in executable.Rui Ueyama2014-03-043-50/+105
| | | | | | | | | | | | | | | | | | The original code does not work correctly on executable files because the code is written in such a way that only object files are assumed to be given to llvm-objdump. Contents of RuntimeFunction are different between executables and objects. In executables, fields in RuntimeFunction have actual addresses to unwind info structures. On the other hand, in object files, the fields have zero value, but instead there are relocations pointing to the fields, so that Linker will fill them at link-time. So, when we are reading an object file, we need to use relocation info to find the location of unwind info. When executable, we should just look at the values in RuntimeFunction. llvm-svn: 202785
* Make a test for llvm-objdump a little bit more readable.Rui Ueyama2014-03-041-44/+44
| | | | llvm-svn: 202783
* [AArch64]Fix improper diagnostics about offset range of load/store instructions.Kevin Qin2014-03-041-32/+32
| | | | llvm-svn: 202775
* MC: Fix Intel assembly parser for [global + offset]Reid Kleckner2014-03-041-0/+9
| | | | | | | | | We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. llvm-svn: 202774
* Revert "[AArch64] This is a work in progress to provide a machine description"Chad Rosier2014-03-041-83/+0
| | | | | | This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. llvm-svn: 202773
* [AArch64] This is a work in progress to provide a machine descriptionChad Rosier2014-03-031-0/+83
| | | | | | | | | | | | | | | | | | | for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 202767
* Pass to emit DWARF path discriminators.Diego Novillo2014-03-033-0/+212
| | | | | | | | | | | | | | | | DWARF discriminators are used to distinguish multiple control flow paths on the same source location. When this happens, instructions across basic block boundaries will share the same debug location. This pass detects this situation and creates a new lexical scope to one of the two instructions. This lexical scope is a child scope of the original and contains a new discriminator value. This discriminator is then picked up from MCObjectStreamer::EmitDwarfLocDirective to be written on the object file. This fixes http://llvm.org/bugs/show_bug.cgi?id=18270. llvm-svn: 202752
* Add DWARF discriminator support to DILexicalBlocks.Diego Novillo2014-03-031-0/+63
| | | | | | This adds support for emitting discriminators from DILexicalBlocks. llvm-svn: 202736
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-035-31/+62
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
* [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug dataEd Maste2014-03-031-0/+43
| | | | | | | | | This fixes invalid lengths in .debug_aranges on big-endian mips64 (lengths appear to be left-shifted by 32 bits) and in .debug_loc. Differential Revision: http://llvm-reviews.chandlerc.com/D2517 llvm-svn: 202716
* [msan] Handle X86 SIMD bitshift intrinsics.Evgeniy Stepanov2014-03-031-0/+100
| | | | llvm-svn: 202712
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-035-1/+23
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. llvm-svn: 202706
* AsmParser: add missed testsSaleem Abdulrasool2014-03-031-0/+22
| | | | | | The diagnostics tests were missing from the previous introduction of ifeqs. llvm-svn: 202674
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-021-0/+7
| | | | | | backend. llvm-svn: 202670
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-023-0/+8
| | | | llvm-svn: 202666
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-021-0/+9
| | | | llvm-svn: 202663
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-022-0/+21
| | | | llvm-svn: 202661
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-021-0/+4
| | | | llvm-svn: 202660
* Add a PPC inline asm constraint type for single CR bitsHal Finkel2014-03-021-0/+59
| | | | | | | | | | | | | | | | | Now that the PowerPC backend can track individual CR bits as first-class registers, we should also have a way of allocating them for inline asm statements. Because these registers are only one bit, if an output variable is implicitly cast to a larger integer size, we'll get an any_extend to that larger type (this is part of the existing target-independent logic). As a result, regardless of the size of the output type, only the first bit is meaningful. The constraint identifier "wc" has been chosen for this purpose. Although gcc does not currently support allocating individual CR bits, this identifier choice has been coordinated with the gcc PowerPC team, and will be marked as reserved for this purpose in the gcc constraints.md file. llvm-svn: 202657
* Ensure bitcode encoding of instructions and their operands stays stable.Michael Kuperstein2014-03-026-0/+467
| | | | | | | | This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls. Work was done by lama.saba@intel.com. llvm-svn: 202647
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-021-0/+78
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-021-6/+18
| | | | llvm-svn: 202624
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-021-42/+67
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-023-6/+21
| | | | llvm-svn: 202610
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-011-0/+878
| | | | llvm-svn: 202602
* R600: Add failing control flow tests.Matt Arsenault2014-03-015-0/+319
| | | | | | Simple cases hit a variety of problems at -O0. llvm-svn: 202601
* Remove extra truncs/exts around i32 bit operations on PPC64Hal Finkel2014-03-011-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | This generalizes the code to eliminate extra truncs/exts around i1 bit operations to also do the same on PPC64 for i32 bit operations. This eliminates a fairly prevalent code wart: int foo(int a) { return a == 5 ? 7 : 8; } On PPC64, because of the extension implied by the ABI, this would generate: cmplwi 0, 3, 5 li 12, 8 li 4, 7 isel 3, 4, 12, 2 rldicl 3, 3, 0, 32 blr where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At least for the single-BB case (which is all that the DAG combine mechanism can handle), this unnecessary extension is no longer generated. llvm-svn: 202600
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-011-0/+116
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-011-0/+23
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+48
| | | | llvm-svn: 202597
* Add missing FileCheck in test command line.Sasa Stankovic2014-03-011-1/+1
| | | | llvm-svn: 202594
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-011-0/+2
| | | | llvm-svn: 202581
* [Sparc] Add support to decode negative simm13 operands in the sparc ↵Venkatraman Govindaraju2014-03-011-0/+13
| | | | | | disassembler. llvm-svn: 202578
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-011-0/+3
| | | | llvm-svn: 202577
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-011-0/+154
| | | | llvm-svn: 202575
* Add support for parsing sun-style section flags in ELFAsmParser.Venkatraman Govindaraju2014-03-011-1/+1
| | | | llvm-svn: 202573
* [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just ↵Venkatraman Govindaraju2014-03-011-0/+11
| | | | | | filling with zeroes. llvm-svn: 202572
* [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.Venkatraman Govindaraju2014-03-011-0/+49
| | | | llvm-svn: 202571
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-013-2/+29
| | | | llvm-svn: 202564
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ↵Venkatraman Govindaraju2014-03-014-3/+12
| | | | | | readability of the generated code. llvm-svn: 202563
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