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* Don't run RAFast in the optimizing regalloc pipeline.Jakob Stoklund Olesen2012-06-0823-24/+24
| | | | | | | | | | | The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. llvm-svn: 158242
* canonicalize:Nuno Lopes2012-06-081-0/+24
| | | | | | | | | | | | | | -%a + 42 into 42 - %a previously we were emitting: -(%a + 42) This fixes the infinite loop in PR12338. The generated code is still not perfect, though. Will work on that next llvm-svn: 158237
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-082-2/+2
| | | | | | | | | | | | | | | | | | | | | | Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! llvm-svn: 158223
* Test case for r158160Manman Ren2012-06-081-0/+42
| | | | llvm-svn: 158218
* Fix a crash in APInt::lshr when shiftAmt > BitWidth.Chad Rosier2012-06-081-0/+8
| | | | | | Patch by James Benton <jbenton@vmware.com>. llvm-svn: 158213
* test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.NAKAMURA Takumi2012-06-081-0/+1
| | | | llvm-svn: 158209
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-082-2/+2
| | | | | | | | | | The pass itself works well, but the something in the Machine* infrastructure does not understand terminators which define registers. Without the ability to use the block-placement pass, etc. this causes performance regressions (and so is turned off by default). Turning off the analysis turns off the problems with the Machine* infrastructure. llvm-svn: 158206
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-081-0/+87
| | | | | | | | | The code which tests for an induction operation cannot assume that any ADDI instruction will have a register operand because the operand could also be a frame index; for example: %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16 llvm-svn: 158205
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel2012-06-081-0/+78
| | | | | | | | | | CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. llvm-svn: 158204
* Revert commit 158073 while waiting for a fix. The issue is that reassociateDuncan Sands2012-06-081-0/+21
| | | | | | | | | | | | | | | | can move instructions within the instruction list. If the instruction just happens to be the one the basic block iterator is pointing to, and it is moved to a different basic block, then we get into an infinite loop due to the iterator running off the end of the basic block (for some reason this doesn't fire any assertions). Original commit message: Grab-bag of reassociate tweaks. Unify handling of dead instructions and instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. llvm-svn: 158199
* X86: optimize generated code for integer ABSManman Ren2012-06-071-6/+10
| | | | | | | | | | | | | | | | | | | | This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 llvm-svn: 158175
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector ↵Nadav Rotem2012-06-071-0/+11
| | | | | | elements, which may disagree with the select condition type. llvm-svn: 158166
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-1/+1
| | | | | | Fixes pr13048. llvm-svn: 158158
* Adding a missing -S to the opt invocation.Meador Inge2012-06-071-1/+1
| | | | llvm-svn: 158128
* X86: replace SUB with CMP if possibleManman Ren2012-06-071-0/+11
| | | | | | | | | | | | | | | | | This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 llvm-svn: 158126
* Spell optimization name correclty.Bill Wendling2012-06-061-1/+1
| | | | llvm-svn: 158123
* Revert r157755.Manman Ren2012-06-061-11/+0
| | | | | | | | The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. llvm-svn: 158122
* Another testcase for r156548.Bill Wendling2012-06-061-0/+162
| | | | | | <rdar://problem/10889741> llvm-svn: 158121
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-06-063-2/+170
| | | | | | | X86. rdar://11496434 llvm-svn: 158087
* Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier2012-06-061-0/+10
| | | | | | | matter. rdar://11579835 llvm-svn: 158084
* Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands2012-06-061-4/+6
| | | | | | | | | instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. llvm-svn: 158073
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-1/+10
| | | | llvm-svn: 158055
* Remove extraneous CHECK-NOTs from previous commit and add a new test case.Chad Rosier2012-06-061-2/+10
| | | | llvm-svn: 158045
* FileCheckize this test.Chad Rosier2012-06-061-2/+18
| | | | llvm-svn: 158044
* Revert commit r157966Joel Jones2012-06-051-19/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+19
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* When gvn decides to replace an instruction with another, we have to patch theRafael Espindola2012-06-044-0/+306
| | | | | | | | | | | | replacement to make it at least as generic as the instruction being replaced. This includes: * dropping nsw/nuw flags * getting the least restrictive tbaa and fpmath metadata * merging ranges Fixes PR12979. llvm-svn: 157958
* Add a test case for mips64 unaligned load/store instructions.Akira Hatanaka2012-06-041-0/+73
| | | | llvm-svn: 157939
* Rename test/CodeGen/Mips/load-shift-left-right.ll.Akira Hatanaka2012-06-041-0/+0
| | | | llvm-svn: 157938
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-0/+16
| | | | llvm-svn: 157935
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-0415-22/+22
| | | | llvm-svn: 157925
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-042-3/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. llvm-svn: 157911
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-031-1/+1
| | | | llvm-svn: 157903
* Rename fma4 intrinsics to just fma since they are now used for both FMA4 and ↵Craig Topper2012-06-032-148/+148
| | | | | | FMA3. Autoupgrade support coming in a separate commit. llvm-svn: 157898
* Revert r157831Manman Ren2012-06-031-19/+0
| | | | llvm-svn: 157896
* Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit ↵Craig Topper2012-06-031-2/+2
| | | | | | loads to match instruction behavior. llvm-svn: 157895
* ARM: add testing case for struct byvalManman Ren2012-06-021-0/+32
| | | | | | rdar://9877866 llvm-svn: 157876
* Add another test case which tests Mips' unaligned load/store instructions.Akira Hatanaka2012-06-021-0/+29
| | | | llvm-svn: 157874
* Fix test cases in test/CodeGen/Mips.Akira Hatanaka2012-06-023-25/+17
| | | | llvm-svn: 157868
* Use dominates(Instruction, Use) in the verifier.Rafael Espindola2012-06-011-2/+2
| | | | | | | This removes a bit of context from the verifier erros, but reduces code duplication in a fairly critical part of LLVM and makes dominates easier to test. llvm-svn: 157845
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-011-0/+19
| | | | | | | | | | | | | | | This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. llvm-svn: 157831
* Add some tests checking that the verifier rejects cases where a definitionRafael Espindola2012-06-011-0/+57
| | | | | | doesn't dominate a use. llvm-svn: 157829
* testcase for PR13006, thanks to Duncan for filing it.Chris Lattner2012-06-011-0/+7
| | | | llvm-svn: 157824
* BoundsChecking: fix a bug when the handling of recursive PHIs failed and ↵Nuno Lopes2012-06-012-1/+49
| | | | | | | | | | could leave dangling references in the cache add regression tests for this problem. Can already compile & run: PHP, PCRE, and ICU (i.e., all the software I tried) llvm-svn: 157822
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-012-0/+79
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying ↵Craig Topper2012-06-011-66/+0
| | | | | | attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. llvm-svn: 157804
* enhance the logic for looking through tailcalls to look through transparent ↵Chris Lattner2012-06-011-0/+46
| | | | | | | | | casts in multiple-return value scenarios, like what happens on X86-64 when returning small structs. llvm-svn: 157800
* enhance getNoopInput to know about vector<->vector bitcasts of legalChris Lattner2012-06-011-0/+22
| | | | | | | | types, as well as int<->ptr casts. This allows us to tailcall functions with some trivial casts between the call and return (i.e. because the return types disagree). llvm-svn: 157798
* add some simple 64-bit tail call tests.Chris Lattner2012-06-011-0/+21
| | | | llvm-svn: 157797
* merge some tests.Chris Lattner2012-06-013-13/+13
| | | | llvm-svn: 157795
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