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* ARM: locate user-defined text sections next to default text.Jim Grosbach2012-10-041-0/+21
| | | | | | | | | | | | Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 llvm-svn: 165254
* Update this a bit more to represent how the prologue should work:Eric Christopher2012-10-041-0/+35
| | | | | | | | | | a) frame setup instructions define the prologue b) we shouldn't change our location mid-stream Add a test to make sure that the stack adjustment stays within the prologue. llvm-svn: 165250
* SimplifyCFG: Enhance the "remove CFG edge that leads to null pointer ↵Benjamin Kramer2012-10-041-0/+28
| | | | | | | | | | dereference" optimization to also handle instructions with multiple uses. We conservatively only check the first use to avoid walking long use chains. This catches the common case of having both a load and a store to a pointer supplied by a PHI node. llvm-svn: 165232
* In my recent change to avoid use of underaligned memory I didn't notice thatDuncan Sands2012-10-041-2/+2
| | | | | | | | cpyDest can be mutated in some cases, which would then cause a crash later if indeed the memory was underaligned. This brought down several buildbots, so I guess the underaligned case is much more common than I thought! llvm-svn: 165228
* The alignment of an sret parameter is known: it must be at least theDuncan Sands2012-10-041-0/+16
| | | | | | alignment of the return type. Teach the optimizers this. llvm-svn: 165226
* Fix PR13969, a mini-phase-ordering issue with the new SROA pass.Chandler Carruth2012-10-041-0/+24
| | | | | | | | | | | | | | | | | | | | | Currently, we re-visit allocas when something changes about the way they might be *split* to allow better scalarization to take place. However, we weren't handling the case when the *promotion* is what would change the behavior of SROA. When an address derived from an alloca is stored into another alloca, we consider the first to have escaped. If the second is ever promoted to an SSA value, we will suddenly be able to run the SROA pass on the first alloca. This patch adds explicit support for this form if iteration. When we detect a store of a pointer derived from an alloca, we flag the underlying alloca for reprocessing after promotion. The logic works hard to only do this when there is definitely going to be promotion and it might remove impediments to the analysis of the alloca. Thanks to Nick for the great test case and Benjamin for some sanity check review. llvm-svn: 165223
* The memcpy optimizer was happily doing call slot forwarding when the new memoryDuncan Sands2012-10-041-3/+21
| | | | | | | | | | was less aligned than the old. In the testcase this results in an overaligned memset: the memset alignment was correct for the original memory but is too much for the new memory. Fix this by either increasing the alignment of the new memory or bailing out if that isn't possible. Should fix the gcc-4.7 self-host buildbot failure. llvm-svn: 165220
* Teach the integer-promotion rewrite strategy to be endianness aware.Chandler Carruth2012-10-046-5/+113
| | | | | | | | | | | | | | | | | | | | | | | Sorry for this being broken so long. =/ As part of this, switch all of the existing tests to be Little Endian, which is the behavior I was asserting in them anyways! Add in a new big-endian test that checks the interesting behavior there. Another part of this is to tighten the rules abotu when we perform the full-integer promotion. This logic now rejects cases where there fully promoted integer is a non-multiple-of-8 bitwidth or cases where the loads or stores touch bits which are in the allocated space of the alloca but are not loaded or stored when accessing the integer. Sadly, these aren't really observable today as the rest of the pass will already ensure the invariants hold. However, the latter situation is likely to become a potential concern in the future. Thanks to Benjamin and Duncan for early review of this patch. I'm still looking into whether there are further endianness issues, please let me know if anyone sees BE failures persisting past this. llvm-svn: 165219
* Implement methods that enable expansion of load immediate Jack Carter2012-10-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic llvm-svn: 165199
* This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter2012-10-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic llvm-svn: 165194
* Fix PR13967.Jakub Staszak2012-10-031-0/+26
| | | | llvm-svn: 165187
* [ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier2012-10-031-0/+14
| | | | | | | | | | | in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. llvm-svn: 165173
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-031-0/+31
| | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. llvm-svn: 165148
* Implement .rel relocation for R_ARM_ABS32 in MCJIT.Tim Northover2012-10-031-0/+16
| | | | | | Patch by Amara Emerson. llvm-svn: 165128
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-031-0/+273
| | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125
* tsan: update the test for new atomic enumsDmitry Vyukov2012-10-031-80/+80
| | | | llvm-svn: 165109
* tsan: update the test for new atomic enumsDmitry Vyukov2012-10-031-40/+40
| | | | llvm-svn: 165108
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-031-0/+22
| | | | | | not propagate through implicit defs. llvm-svn: 165102
* Fix an issue where we failed to adjust the alignment constraint onChandler Carruth2012-10-031-0/+31
| | | | | | | | a memcpy to reflect that '0' has a different meaning when applied to a load or store. Now we correctly use underaligned loads and stores for the test case added. llvm-svn: 165101
* Try to use a better set of abstractions for computing the alignmentChandler Carruth2012-10-031-4/+59
| | | | | | | | | | | | | | | | | | | | necessary during rewriting. As part of this, fix a real think-o here where we might have left off an alignment specification when the address is in fact underaligned. I haven't come up with any way to trigger this, as there is always some other factor that reduces the alignment, but it certainly might have been an observable bug in some way I can't think of. This also slightly changes the strategy for placing explicit alignments on loads and stores to only do so when the alignment does not match that required by the ABI. This causes a few redundant alignments to go away from test cases. I've also added a couple of tests that really push on the alignment that we end up with on loads and stores. More to come here as I try to fix an underlying bug I have conjectured and produced test cases for, although it's not clear if this bug is the one currently hitting dragonegg's gcc47 bootstrap. llvm-svn: 165100
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-031-65/+0
| | | | | | more detail. llvm-svn: 165099
* test/ExecutionEngine/MCJIT: MCJIT should work also on mingw.NAKAMURA Takumi2012-10-032-2/+2
| | | | | FIXME: Also cygwin? llvm-svn: 165081
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-1/+1
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Fix a serious X86 instruction selection bug. InEvan Cheng2012-10-021-0/+16
| | | | | | | | | | | | | X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 llvm-svn: 165072
* Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher2012-10-021-35/+0
| | | | | | | This reverts 165055 and 165052 temporarily while I look at debugger failures. llvm-svn: 165071
* Teach the new SROA to handle cases where an alloca that has already beenChandler Carruth2012-10-021-0/+29
| | | | | | | | | | | | | | | | scheduled for processing on the worklist eventually gets deleted while we are processing another alloca, fixing the original test case in PR13990. To facilitate this, add a remove_if helper to the SetVector abstraction. It's not easy to use the standard abstractions for this because of the specifics of SetVectors types and implementation. Finally, a nice small test case is included. Thanks to Benjamin for the fantastic reduced test case here! All I had to do was delete some empty basic blocks! llvm-svn: 165065
* Make sure to put our sret argument into %rax on x86-64. Fixes PR13563!Nick Lewycky2012-10-021-0/+13
| | | | llvm-svn: 165063
* Make sure the whole live range is covered when values are pruned twice.Jakob Stoklund Olesen2012-10-021-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | JoinVals::pruneValues() calls LIS->pruneValue() to avoid conflicts when overlapping two different values. This produces a set of live range end points that are used to reconstruct the live range (with SSA update) after joining the two registers. When a value is pruned twice, the set of end points was insufficient: v1 = DEF v1 = REPLACE1 v1 = REPLACE2 KILL v1 The end point at KILL would only reconstruct the live range from REPLACE2 to KILL, leaving the range REPLACE1-REPLACE2 dead. Add REPLACE2 as an end point in this case so the full live range is reconstructed. This fixes PR13999. llvm-svn: 165056
* Allow alternate instructions to silence bot.Eric Christopher2012-10-021-1/+1
| | | | llvm-svn: 165055
* Don't use a debug location for frame setup instructions in theEric Christopher2012-10-021-0/+35
| | | | | | | prologue. Also skip frame setup instructions when looking for the first location. llvm-svn: 165052
* Remove the SavePoint infrastructure from fast isel, replaceEric Christopher2012-10-021-0/+65
| | | | | | | with just an insert point from the MachineBasicBlock and let the location be updated as we access it. llvm-svn: 165049
* Support for generating ELF objects on Windows.Andrew Kaylor2012-10-0250-49/+56
| | | | | | This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present. This patch also enables MCJIT tests on Windows using the new environment value. llvm-svn: 165030
* Fix broken tests.Benjamin Kramer2012-10-024-5/+6
| | | | llvm-svn: 165019
* Fix PR13991: legalizing an overflowing multiplication operation is harder thanDuncan Sands2012-10-021-0/+14
| | | | | | | the add/sub case since in the case of multiplication you also have to check that the operation in the larger type did not overflow. llvm-svn: 165017
* Add default JIT LIT variable.James Molloy2012-10-024-3/+8
| | | | | | Patch by David Tweed! llvm-svn: 164996
* test/CodeGen/X86/red-zone2.ll: Add -mtriple=x86_64-linux, and FileCheck-ize.NAKAMURA Takumi2012-10-011-3/+4
| | | | llvm-svn: 164975
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-012-1/+109
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. llvm-svn: 164974
* checking test case for r164811. was an omission to not check this in. this ↵Reed Kotler2012-10-011-0/+41
| | | | | | was already approved llvm-svn: 164972
* Forgot the SPIR test case.Micah Villmow2012-10-011-0/+13
| | | | llvm-svn: 164949
* Fix PR13899Michael Liao2012-10-011-0/+58
| | | | | | | | | - Update maximal stack alignment when stack arguments are prepared before a call. - Test cases are enhanced to show it's not a Win32 specific issue but a generic one. llvm-svn: 164946
* Fix more misspellings found by Duncan during review.Chandler Carruth2012-10-011-2/+2
| | | | llvm-svn: 164940
* Fix several issues with alignment. We weren't always accounting for typeChandler Carruth2012-10-011-0/+31
| | | | | | | | | | alignment requirements of the new alloca. As one consequence which was reported as a bug by Duncan, we overaligned memcpy calls to ranges of allocas after they were rewritten to types with lower alignment requirements. Other consquences are possible, but I don't have any test cases for them. llvm-svn: 164937
* SimplifyCFG: Don't crash when forming a switch bitmap with an undef default ↵Benjamin Kramer2012-10-011-0/+24
| | | | | | | | value. Fixes PR13985. llvm-svn: 164934
* Refactor the PartitionUse structure to actually use the Use* instead ofChandler Carruth2012-10-011-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a pair of instructions, one for the used pointer and the second for the user. This simplifies the representation and also makes it more dense. This was noticed because of the miscompile in PR13926. In that case, we were running up against a fundamental "bad idea" in the speculation of PHI and select instructions: the speculation and rewriting are interleaved, which requires phi speculation to also perform load rewriting! This is bad, and causes us to miss opportunities to do (for example) vector rewriting only exposed after PHI speculation, etc etc. It also, in the old system, required us to insert *new* load uses into the current partition's use list, which would then be ignored during rewriting because we had already extracted an end iterator for the use list. The appending behavior (and much of the other oddities) stem from the strange de-duplication strategy in the PartitionUse builder. Amusingly, all this went without notice for so long because it could only be triggered by having *different* GEPs into the same partition of the same alloca, where both different GEPs were operands of a single PHI, and where the GEP which was not encountered first also had multiple uses within that same PHI node... Hence the insane steps required to reproduce. So, step one in fixing this fundamental bad idea is to make the PartitionUse actually contain a Use*, and to make the builder do proper deduplication instead of funky de-duplication. This is enough to remove the appending behavior, and fix the miscompile in PR13926, but there is more work to be done here. Subsequent commits will lift the speculation into its own visitor. It'll be a useful step toward potentially extracting all of the speculation logic into a generic utility transform. The existing PHI test case for repeated operands has been made more extreme to catch even these issues. This test case, run through the old pass, will exactly reproduce the miscompile from PR13926. ;] We were so close here! llvm-svn: 164925
* Ignore apparent buffer overruns on external or weak globals. This is a majorDuncan Sands2012-09-301-0/+5
| | | | | | | source of false positives due to globals being declared in a header with some kind of incomplete (small) type, but the actual definition being bigger. llvm-svn: 164912
* Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem2012-09-304-158/+12
| | | | llvm-svn: 164911
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-304-12/+158
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164910
* Add LLVM support for Swift.Bob Wilson2012-09-2926-35/+224
| | | | llvm-svn: 164899
* Whitespace.Bob Wilson2012-09-291-2/+2
| | | | llvm-svn: 164898
* Fix a somewhat surprising miscompile where code relying on an ABIChandler Carruth2012-09-291-1/+22
| | | | | | | | | | | | | | | alignment could lose it due to the alloca type moving down to a much smaller alignment guarantee. Now SROA will actively compute a proper alignment, factoring the target data, any explicit alignment, and the offset within the struct. This will in some cases lower the alignment requirements, but when we lower them below those of the type, we drop the alignment entirely to give freedom to the code generator to align it however is convenient. Thanks to Duncan for the lovely test case that pinned this down. =] llvm-svn: 164891
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