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* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-0/+12
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* Fix rdar://9289512 - not folding load into compare at -O0Chris Lattner2011-04-171-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
* Remove working entry from README.Eli Friedman2011-04-171-1/+1
| | | | llvm-svn: 129654
* fix rdar://9289583 - fast isel should handle non-canonical commutative binopsChris Lattner2011-04-171-0/+14
| | | | | | | | | | allowing us to fold the immediate into the 'and' in this case: int test1(int i) { return 8&i; } llvm-svn: 129653
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-0/+23
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Add test cases for Jay's r129641 and fix a 32-bit-centric testcase in a file ↵Frits van Bommel2011-04-161-5/+81
| | | | | | with a 64-bit datalayout. llvm-svn: 129643
* Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand ↵Evan Cheng2011-04-161-0/+31
| | | | | | the node to a libcall. rdar://9280991 llvm-svn: 129633
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+11
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* Re-enable test o32_cc_vararg.ll.Akira Hatanaka2011-04-151-3/+0
| | | | llvm-svn: 129616
* Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generateCameron Zwarich2011-04-151-3/+22
| | | | | | a case involving EOR, so I only added a test for ORR. llvm-svn: 129610
* Add this test back for Darwin.Rafael Espindola2011-04-151-0/+10
| | | | llvm-svn: 129607
* The AND instruction leaves the V flag unmodified, so it falls victim to the sameCameron Zwarich2011-04-151-0/+22
| | | | | | problem as all of the other instructions we fold with CMPs. llvm-svn: 129602
* Add missing register forms of instructions to the ARM CMP-folding code. ThisCameron Zwarich2011-04-151-0/+22
| | | | | | fixes <rdar://problem/9287901>. llvm-svn: 129599
* Add pass that expands pseudo instructions into target instructions after ↵Akira Hatanaka2011-04-152-0/+30
| | | | | | register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
* Add encoding tests for flds/fildsJoerg Sonnenberger2011-04-152-0/+24
| | | | llvm-svn: 129589
* Add 129518 back with a fix for when we are producing eh just because of ↵Rafael Espindola2011-04-153-15/+4
| | | | | | | | | debug info. Change ELF systems to use CFI for producing the EH tables. This reduces the size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129571
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-1515-16/+16
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Revert r129518, "Change ELF systems to use CFI for producing the EH tables. ↵NAKAMURA Takumi2011-04-153-4/+15
| | | | | | | | This reduces the" It broke several builds. llvm-svn: 129557
* Fix another fcopysign lowering bug. If src is f64 and destination is f32, don'tEvan Cheng2011-04-151-4/+21
| | | | | | forget to right shift the source by 32 first. rdar://9287902 llvm-svn: 129556
* Add 3DNow! intrinsics.Michael J. Spencer2011-04-151-0/+297
| | | | llvm-svn: 129551
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-152-0/+16
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-0/+56
| | | | llvm-svn: 129548
* Add an instcombine for constructs like a | -(b != c); a select is moreEli Friedman2011-04-141-0/+19
| | | | | | | canonical, and generally leads to better code. Found while looking at an article about saturating arithmetic. llvm-svn: 129545
* Fix an infinite alternation in JumpThreading where two transforms would ↵Owen Anderson2011-04-141-0/+31
| | | | | | | | | | repeatedly undo each other. The solution is to perform more aggressive constant folding to make one of the edges just folded away rather than trying to thread it. Fixes <rdar://problem/9284786>. Discovered with CSmith. llvm-svn: 129538
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-144-0/+33
| | | | | | operations. llvm-svn: 129531
* tests: Remove a FrontendC test which is no longer valid.Daniel Dunbar2011-04-141-11/+0
| | | | llvm-svn: 129519
* Change ELF systems to use CFI for producing the EH tables. This reduces theRafael Espindola2011-04-143-15/+4
| | | | | | size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129518
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-145-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-1428-108/+99
| | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-1431-152/+161
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Vectors with different number of elements of the same element type can haveMon P Wang2011-04-131-0/+46
| | | | | | | | the same allocation size but different primitive sizes(e.g., <3xi32> and <4xi32>). When ScalarRepl promotes them, it can't use a bit cast but should use a shuffle vector instead. llvm-svn: 129472
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-132-2/+13
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-0/+18
| | | | llvm-svn: 129468
* Fix a regression caused by r102515 where explicit alignment on globals isCameron Zwarich2011-04-132-5/+5
| | | | | | | ignored. There was a test to catch this, but it was just blindly updated in a large change. This fixes another part of <rdar://problem/9275290>. llvm-svn: 129466
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-132-0/+20
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Fix an obvious problem with an alignment computation. AsmPrinter actually doesCameron Zwarich2011-04-131-0/+2
| | | | | | | the max itself, so it is not easy to write a test case for this, but I added a test case that would fail if the code in AsmPrinter were removed. llvm-svn: 129432
* If a global variable has a specified alignment that is less than the preferredCameron Zwarich2011-04-131-0/+9
| | | | | | | alignment for its type, use the minimum of the specified alignment and the ABI alignment. This fixes <rdar://problem/9275290>. llvm-svn: 129428
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-136-27/+25
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Reapply r129401 with patch for clang.Bill Wendling2011-04-132-2/+14
| | | | llvm-svn: 129419
* Temporarily revert r129408 to see if it brings the bots back.Eric Christopher2011-04-131-15/+0
| | | | llvm-svn: 129417
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-121-0/+15
| | | | | | | | registers for fast allocation. Fixes rdar://9207598 llvm-svn: 129408
* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-122-14/+2
| | | | llvm-svn: 129403
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-122-2/+14
| | | | | | | | | Now that we have a first-class way to represent unaligned loads, the unaligned load intrinsics are superfluous. First part of <rdar://problem/8460511>. llvm-svn: 129401
* Fix compiler command line used by lit.py when working with NMakeOscar Fuentes2011-04-121-2/+20
| | | | | | | | generators. It may improve robustness when testing from VS too. Based on a patch by David Neto! llvm-svn: 129398
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
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