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* [WinEH] Emit .safeseh directives for all 32-bit exception handlersReid Kleckner2015-06-102-0/+6
| | | | | | | | | | Use a "safeseh" string attribute to do this. You would think we chould just accumulate the set of personalities like we do on dwarf, but this fails to account for the LSDA-loading thunks we use for __CxxFrameHandler3. Each of those needs to make it into .sxdata as well. The string attribute seemed like the most straightforward approach. llvm-svn: 239448
* Add explicit -mtriple=arm-unknown to ↵NAKAMURA Takumi2015-06-091-3/+3
| | | | | | llvm/test/CodeGen/ARM/disable-tail-calls.ll, to satisfy *-win32. llvm-svn: 239442
* [BasicBlockUtils] Set debug locations for instructions created in ↵Alexey Samsonov2015-06-091-0/+90
| | | | | | | | | | | | | | SplitBlockPredecessors. Test Plan: regression test suite Reviewers: eugenis, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10343 llvm-svn: 239438
* Move dllimport name mangling to IR mangler.Peter Collingbourne2015-06-091-0/+17
| | | | | | | | This ensures that LTO clients see the correct external symbol name. Differential Revision: http://reviews.llvm.org/D10318 llvm-svn: 239437
* [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpacesJingyue Wu2015-06-091-0/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: We used to assume V->RAUW only modifies the operand list of V's user. However, if V and V's user are Constants, RAUW may replace and invalidate V's user entirely. This patch fixes the above issue by letting the caller replace the operand instead of calling RAUW on Constants. Test Plan: @nested_const_expr and @rauw in access-non-generic.ll Reviewers: broune, jholewinski Reviewed By: broune, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10345 llvm-svn: 239435
* LibDriver, llvm-lib: introduce.Peter Collingbourne2015-06-093-0/+11
| | | | | | | | | | llvm-lib is intended to be a lib.exe compatible utility that also understands bitcode. The implementation lives in a library so that lld can use it to implement /lib. Differential Revision: http://reviews.llvm.org/D10297 llvm-svn: 239434
* [WinEH] Add 32-bit SEH state table emission prototypeReid Kleckner2015-06-093-14/+225
| | | | | | | | | | | | This gets all the handler info through to the asm printer and we can look at the .xdata tables now. I've convinced one small catch-all test case to work, but other than that, it would be a stretch to say this is functional. The state numbering algorithm avoids doing any scope reconstruction as we do for C++ to simplify the implementation. llvm-svn: 239433
* [AArch64] Remove an overly conservative check when generating store pairs.Chad Rosier2015-06-091-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Store instructions do not modify register values and therefore it's safe to form a store pair even if the source register has been read in between the two store instructions. Previously, the read of w1 (see below) prevented the formation of a stp. str w0, [x2] ldr w8, [x2, #8] add w0, w8, w1 str w1, [x2, #4] ret We now generate the following code. stp w0, w1, [x2] ldr w8, [x2, #8] add w0, w8, w1 ret All correctness tests with -Ofast on A57 with Spec200x and EEMBC pass. Performance results for SPEC2K were within noise. llvm-svn: 239432
* Remove DisableTailCalls from TargetOptions and the code in resetTargetOptionsAkira Hatanaka2015-06-092-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | that was resetting it. Remove the uses of DisableTailCalls in subclasses of TargetLowering and use the value of function attribute "disable-tail-calls" instead. Also, unconditionally add pass TailCallElim to the pipeline and check the function attribute at the start of runOnFunction to disable the pass on a per-function basis. This is part of the work to remove TargetMachine::resetTargetOptions, and since DisableTailCalls was the last non-fast-math option that was being reset in that function, we should be able to remove the function entirely after the work to propagate IR-level fast-math flags to DAG nodes is completed. Out-of-tree users should remove the uses of DisableTailCalls and make changes to attach attribute "disable-tail-calls"="true" or "false" to the functions in the IR. rdar://problem/13752163 Differential Revision: http://reviews.llvm.org/D10099 llvm-svn: 239427
* MergeFunctions: Don't replace a weak function use by another equivalent weak ↵Arnold Schwaighofer2015-06-091-9/+39
| | | | | | | | | | function We don't know whether the weak functions definition is the definitive definition. rdar://21303727 llvm-svn: 239422
* Revert "[DWARF] Fix a few corner cases in expression emission"David Blaikie2015-06-091-110/+0
| | | | | | | This reverts commit r239380 due to apparently GDB regressions: http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/22562 llvm-svn: 239420
* The constant initialization for globals in NVPTX is generated as an Samuel Antao2015-06-091-0/+23
| | | | | | | | | | array of bytes. The generation of this byte arrays was expecting the host to be little endian, which prevents big endian hosts to be used in the generation of the PTX code. This patch fixes the problem by changing the way the bytes are extracted so that it works for either little and big endian. llvm-svn: 239412
* Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-092-0/+26
| | | | | | | Specified the llvm namespace for the 2 calls to make_unique() which caused compilation errors in Visual Studio 2013. llvm-svn: 239405
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+38
| | | | | | Added encoding tests. llvm-svn: 239403
* Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." ↵Toma Tabacu2015-06-094-158/+0
| | | | | | | | (r239396). It was breaking buildbots. llvm-svn: 239397
* [mips] [IAS] Add support for BNE and BEQ with an immediate operand.Toma Tabacu2015-06-094-0/+158
| | | | | | | | | | | | | | | | Summary: For some branches, GAS accepts an immediate instead of the 2nd register operand. We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9666 llvm-svn: 239396
* llvm/test/DebugInfo/X86/expressions.ll: %llc_dwarf shouldn't be used with ↵NAKAMURA Takumi2015-06-091-2/+2
| | | | | | | | -mtriple, since %llc_dwarf implies the triple. In this case, use plain "llc". llvm-svn: 239390
* Move X86-only test case to appropriate directoryKeno Fischer2015-06-091-0/+0
| | | | llvm-svn: 239384
* [DWARF] Fix a few corner cases in expression emissionKeno Fischer2015-06-091-0/+110
| | | | | | | | | | | | | | | | | | | Summary: I noticed an object file with `DW_OP_reg4 DW_OP_breg4 0` as a DWARF expression, which I traced to a missing break (and `++I`) in this code snippet. While I was at it, I also added support for a few other corner cases along the same lines that I could think of. Test Plan: Hand-crafted test case to exercises these cases is included. Reviewers: echristo, dblaikie, aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10302 llvm-svn: 239380
* [asan] Prevent __attribute__((annotate)) triggering errors on DarwinAnna Zaks2015-06-091-0/+12
| | | | | | | | | | | | | | | | | The following code triggers a fatal error in the compiler instrumentation of ASan on Darwin because we place the attribute into llvm.metadata section, which does not have the proper MachO section name. void foo() __attribute__((annotate("custom"))); void foo() {;} This commit reorders the checks so that we skip everything in llvm.metadata first. It also removes the hard failure in case the section name does not parse. That check will be done lower in the compilation pipeline anyway. (Reviewed in http://reviews.llvm.org/D9093.) llvm-svn: 239379
* Implement computeKnownBits for min/max nodesMatt Arsenault2015-06-093-4/+103
| | | | llvm-svn: 239378
* [NVPTX] run SROA after NVPTXFavorNonGenericAddrSpacesJingyue Wu2015-06-091-2/+3
| | | | | | | | | | | | | | | | | | Summary: This cleans up most allocas NVPTXLowerKernelArgs emits for byval parameters. Test Plan: makes bug21465.ll more stronger to verify no redundant local load/store. Reviewers: eliben, jholewinski Reviewed By: eliben, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10322 llvm-svn: 239368
* MergeFunctions: Impose a total order on the replacement of functionsArnold Schwaighofer2015-06-092-4/+34
| | | | | | | | | | | | | We don't want to replace function A by Function B in one module and Function B by Function A in another module. If these functions are marked with linkonce_odr we would end up with a function stub calling B in one module and a function stub calling A in another module. If the linker decides to pick these two we will have two stubs calling each other. rdar://21265586 llvm-svn: 239367
* [AArch64] AsmParser should be case insensitive about accepting vector ↵Ranjeet Singh2015-06-081-0/+8
| | | | | | | | register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
* Fix a regression in .pop_section.Rafael Espindola2015-06-081-0/+21
| | | | | | | It was calling ChangeSection with the wrong current section, eventually leading to a crash. llvm-svn: 239335
* [X86][SSE] Added lzcnt vector tests.Simon Pilgrim2015-06-082-0/+3010
| | | | llvm-svn: 239333
* [ARM] Pass a callback to FunctionPass constructors to enable skipping executionAkira Hatanaka2015-06-081-0/+22
| | | | | | | | | | | | | | | | on a per-function basis. Previously some of the passes were conditionally added to ARM's pass pipeline based on the target machine's subtarget. This patch makes changes to add those passes unconditionally and execute them conditonally based on the predicate functor passed to the pass constructors. This enables running different sets of passes for different functions in the module. rdar://problem/20542263 Differential Revision: http://reviews.llvm.org/D8717 llvm-svn: 239325
* X86: Reject register operands with obvious type mismatches.Matthias Braun2015-06-081-0/+10
| | | | | | | | | | | | | While we have some code to transform specification like {ax} into {eax}/{rax} if the operand type isn't 16bit, we should reject cases where there is no sane way to do this, like the i128 type in the example. Related to rdar://21042280 Differential Revision: http://reviews.llvm.org/D10260 llvm-svn: 239309
* [Hexagon] Adding functionality for searching for compound instruction pairs. ↵Colin LeMahieu2015-06-081-0/+17
| | | | | | Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. llvm-svn: 239307
* [DAGCombiner] Added CTLZ vector constant folding support.Simon Pilgrim2015-06-082-0/+210
| | | | llvm-svn: 239305
* ARM]: Add support for MMFR4_EL1 in assemblerJaved Absar2015-06-083-0/+8
| | | | | | | This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler. This register provides information about the implemented memory model and memory management support. llvm-svn: 239302
* [Mips64][mcjit] Add R_MIPS_PC32 relocationPetar Jovanovic2015-06-081-0/+9
| | | | | | | | | | This patch adds R_MIPS_PC32 relocation for Mips64. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10235 llvm-svn: 239301
* AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNLIgor Breger2015-06-083-0/+263
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for DAG lowering and encoding. Differential Revision: http://reviews.llvm.org/D10310 llvm-svn: 239300
* Minor refactoring of GEP handling in isDereferenceablePointerArtur Pilipenko2015-06-081-0/+13
| | | | | | | | | | For GEP instructions isDereferenceablePointer checks that all indices are constant and within bounds. Replace this index calculation logic to a call to accumulateConstantOffset. Separated from the http://reviews.llvm.org/D9791 Reviewed By: sanjoy Differential Revision: http://reviews.llvm.org/D9874 llvm-svn: 239299
* [LAA] Fix estimation of number of memchecksSilviu Baranga2015-06-081-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We need to add a runtime memcheck for pair of accesses (x,y) where at least one of x and y are writes. Assuming we have w writes and r reads, currently this number is estimated as being w* (w+r-1). This estimation will count (write,write) pairs twice and will overestimate the number of checks required. This change adds a getNumberOfChecks method to RuntimePointerCheck, which will count the number of runtime checks needed (similar in implementation to needsAnyChecking) and uses it to produce the correct number of runtime checks. Test Plan: llvm test suite spec2k spec2k6 Performance results: no changes observed (not surprising since the formula for 1 writer is basically the same, which would covers most cases - at least with the current check limit). Reviewers: anemet Reviewed By: anemet Subscribers: mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D10217 llvm-svn: 239295
* [DAGCombiner] Added CTTZ vector constant folding support.Simon Pilgrim2015-06-082-0/+188
| | | | llvm-svn: 239293
* [LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.Hao Liu2015-06-082-20/+484
| | | | | | | | | | | | | | | | | | | | | | | | Interleaved memory accesses are grouped and vectorized into vector load/store and shufflevector. E.g. for (i = 0; i < N; i+=2) { a = A[i]; // load of even element b = A[i+1]; // load of odd element ... // operations on a, b, c, d A[i] = c; // store of even element A[i+1] = d; // store of odd element } The loads of even and odd elements are identified as an interleave load group, which will be transfered into vectorized IRs like: %wide.vec = load <8 x i32>, <8 x i32>* %ptr %vec.even = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %vec.odd = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> The stores of even and odd elements are identified as an interleave store group, which will be transfered into vectorized IRs like: %interleaved.vec = shufflevector <4 x i32> %vec.even, %vec.odd, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> store <8 x i32> %interleaved.vec, <8 x i32>* %ptr This optimization is currently disabled by defaut. To try it by adding '-enable-interleaved-mem-accesses=true'. llvm-svn: 239291
* [LoopAccessAnalysis] Teach LAA to check the memory dependence between ↵Hao Liu2015-06-081-0/+540
| | | | | | | | strided accesses. Differential Revision: http://reviews.llvm.org/D9368 llvm-svn: 239285
* [objdump] Moving PrintImmHex out of MachODump and in to llvm-objdump and ↵Colin LeMahieu2015-06-071-0/+10
| | | | | | setting instprinter appropriately. llvm-svn: 239265
* [X86] Added tzcnt vector tests.Simon Pilgrim2015-06-072-0/+2795
| | | | llvm-svn: 239264
* SeparateConstOffsetFromGEP: Pass address space to isLegalAddressingModeMatt Arsenault2015-06-072-0/+97
| | | | llvm-svn: 239262
* [X86] Added BitScanForward/BitScanReverse memory folding + testsSimon Pilgrim2015-06-071-0/+51
| | | | llvm-svn: 239257
* Fixed line endingsSimon Pilgrim2015-06-072-6/+6
| | | | llvm-svn: 239253
* [DAGCombiner] Added CTPOP vector constant folding support.Simon Pilgrim2015-06-072-0/+92
| | | | | | Added tests to the existing SSE/AVX test files. llvm-svn: 239252
* Teaching llvm-mc how to understand the defsym command line option. This ↵Colin LeMahieu2015-06-073-0/+24
| | | | | | allows integer-constant symbols to be defined on the command line and used during assembly. llvm-svn: 239240
* [MC] Common symbols weren't being checked for redeclaration which allowed an ↵Colin LeMahieu2015-06-062-0/+10
| | | | | | assembly file to generate an assertion in setCommon(): !isCommon(). This change allows redeclaration as long as the size and alignment match exactly, otherwise report a fatal error. llvm-svn: 239227
* [LoopUnroll] Fix truncation bug in canUnrollCompletely.Sanjoy Das2015-06-061-0/+58
| | | | | | | | | | | | | | | | | Summary: canUnrollCompletely takes `unsigned` values for `UnrolledCost` and `RolledDynamicCost` but is passed in `uint64_t`s that are silently truncated. Because of this, when `UnrolledSize` is a large integer that has a small remainder with UINT32_MAX, LLVM tries to completely unroll loops with high trip counts. Reviewers: mzolotukhin, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10293 llvm-svn: 239218
* [CVP] Don't assume Constants of type i1 can be known to be true or falseDavid Majnemer2015-06-061-0/+22
| | | | | | | | | | | | | CVP wants to analyze the condition operand of a select along an edge. It succeeds in getting back a Constant but not a ConstantInt. Instead, it gets a ConstantExpr. It then assumes that the Constant must be equal to false because it isn't equal to true. Instead, perform an additional comparison. This fixes PR23752. llvm-svn: 239217
* [InstCombine] Don't miscompile select to poisonDavid Majnemer2015-06-061-0/+13
| | | | | | | | | | | | | | | | If we have (select a, b, c), it is sometimes valid to simplify this to a single select operand. However, doing so is only valid if the computation doesn't inject poison into the computation. It might be helpful to consider the following example: (select (icmp ne %i, INT_MAX), (add nsw %i, 1), INT_MIN) The select is equivalent to (add %i, 1) but not (add nsw %i, 1). Self hosting on x86_64 revealed that this occurs very, very rarely so bailing out is hopefully pretty reasonable. llvm-svn: 239215
* Handle 16 bit PC relative relocations.Rafael Espindola2015-06-061-0/+5
| | | | | | Fixes pr23771. llvm-svn: 239214
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