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* Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.Lang Hames2012-01-271-0/+21
| | | | llvm-svn: 149097
* Handle call-clobbered ymm registers on Win64.Jakob Stoklund Olesen2012-01-261-0/+48
| | | | | | | | | | | | | | The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. llvm-svn: 149088
* Replace the use of isPredicable() with isPredicated() inChad Rosier2012-01-261-0/+44
| | | | | | | | | MachineBasicBlock::canFallThrough(). We're interested in the state of the instruction (i.e., is this a barrier or not?), not if the instruction is predicable or not. rdar://10501092 llvm-svn: 149070
* Clear kill flags before propagating a copy.Jakob Stoklund Olesen2012-01-261-0/+121
| | | | | | | | | | The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. llvm-svn: 149069
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-0/+12
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* Fix for the following bug in AVX codegen for double-to-int conversions:Victor Umansky2012-01-262-1/+20
| | | | | | | | | | | | | . "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode. . Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode. . Consequently, the conversion produces incorrect numbers. The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows. The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). llvm-svn: 149056
* Improve sub-register def handling in ProcessImplicitDefs.Jakob Stoklund Olesen2012-01-251-0/+24
| | | | | | | | | This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. llvm-svn: 148996
* Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov2012-01-252-16/+24
| | | | | | | | and let linker handle the rest. This finally fixes PR5329 llvm-svn: 148990
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-0/+11
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
* Support pointer comparisons against constants, when looking at the inline-costNick Lewycky2012-01-251-0/+39
| | | | | | | | | savings from a pointer argument becoming an alloca. Sometimes callees will even compare a pointer to null and then branch to an otherwise unreachable block! Detect these cases and compute the number of saved instructions, instead of bailing out and reporting no savings. llvm-svn: 148941
* Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka2012-01-251-2/+2
| | | | | | | | | | | - Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. llvm-svn: 148917
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-251-7/+16
| | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. llvm-svn: 148908
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-0/+40
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+41
| | | | llvm-svn: 148882
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-242-1/+44
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. llvm-svn: 148879
* Pattern for f32 to i64 conversion.Akira Hatanaka2012-01-241-0/+7
| | | | llvm-svn: 148869
* ARM Darwin symbol ref differences w/o subsection-via-symbols.Jim Grosbach2012-01-241-0/+18
| | | | | | | | When not using subsections via symbols, the assembler can resolve symbol differences (including pcrel references) to non-local labels at assembly time, not just those in the same atom. llvm-svn: 148865
* Intel Syntax: Extend special hand coded logic, to recognize special ↵Devang Patel2012-01-241-0/+3
| | | | | | instructions, for intel syntax. llvm-svn: 148864
* 64-bit sign extension in register instructions.Akira Hatanaka2012-01-241-8/+4
| | | | llvm-svn: 148862
* [asan] enable asan only for the functions that have Attribute::AddressSafetyKostya Serebryany2012-01-243-4/+4
| | | | llvm-svn: 148846
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | llvm-svn: 148836
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | llvm-svn: 148832
* Add an (interleave A, B, ...) SetTheory operator.Jakob Stoklund Olesen2012-01-241-0/+7
| | | | | | This will interleave the elements from two or more lists. llvm-svn: 148824
* NEON Two-operand assembly aliases for VSRA.Jim Grosbach2012-01-241-33/+71
| | | | llvm-svn: 148821
* Remove redundant test file.Jim Grosbach2012-01-241-98/+0
| | | | llvm-svn: 148820
* NEON Two-operand assembly aliases for VSLI.Jim Grosbach2012-01-241-16/+33
| | | | llvm-svn: 148819
* NEON Two-operand assembly aliases for VSRI.Jim Grosbach2012-01-241-16/+33
| | | | llvm-svn: 148818
* Tidy up.Jim Grosbach2012-01-241-32/+41
| | | | llvm-svn: 148817
* ZERO_EXTEND operation is optimized for AVX.Elena Demikhovsky2012-01-241-0/+17
| | | | | | v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions. llvm-svn: 148803
* An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov2012-01-241-0/+1
| | | | | | | | This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. llvm-svn: 148800
* Fix the testcases for the previous patch.Eric Christopher2012-01-244-9/+7
| | | | | | rdar://10278198 llvm-svn: 148795
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-17/+39
| | | | llvm-svn: 148764
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-19/+39
| | | | llvm-svn: 148762
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-241-0/+35
| | | | llvm-svn: 148755
* NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-19/+39
| | | | llvm-svn: 148748
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-232-65/+73
| | | | llvm-svn: 148745
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+4
| | | | llvm-svn: 148737
* NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach2012-01-231-11/+33
| | | | llvm-svn: 148734
* Add support for .cfi_signal_frame. Fixes pr11762.Rafael Espindola2012-01-231-0/+23
| | | | llvm-svn: 148733
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-0/+105
| | | | | | This fixes a typo in r148589. llvm-svn: 148724
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-1/+3
| | | | llvm-svn: 148721
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-8/+8
| | | | | | | Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-0/+2
| | | | llvm-svn: 148712
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-2/+3
| | | | | | | | This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. llvm-svn: 148686
* Make Value::isDereferenceablePointer() handle unreachable code blocks. (ThisNick Lewycky2012-01-231-0/+28
| | | | | | | | returns false in the event the computation feeding into the pointer is unreachable, which maybe ought to be true -- but this is at least consistent with undef->isDereferenceablePointer().) Fixes PR11825! llvm-svn: 148671
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+68
| | | | | | Patch by Ana Pazos! llvm-svn: 148658
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-0/+2
| | | | llvm-svn: 148591
* Handle a corner case with IV chain collection with bailout instead of assert.Andrew Trick2012-01-201-0/+43
| | | | | | Fixes PR11783: bad cast to AddRecExpr. llvm-svn: 148572
* Test case comments missing from my previous checkin.Andrew Trick2012-01-201-0/+5
| | | | llvm-svn: 148571
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