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* [X86][SSE] Regenerated comparison mask and float immediate testsSimon Pilgrim2016-04-012-19/+66
| | | | llvm-svn: 265184
* [X86][SSE] Regenerated the vec_extract tests.Simon Pilgrim2016-04-015-180/+431
| | | | llvm-svn: 265183
* [X86][SSE] Regenerated the vec_insert tests.Simon Pilgrim2016-04-019-121/+410
| | | | llvm-svn: 265179
* [X86][SSE] Regenerated vec_partial tests.Simon Pilgrim2016-04-011-10/+11
| | | | llvm-svn: 265173
* [x86] add an SSE2 + fast-unaligned accesses run for memset nonzero testsSanjay Patel2016-04-011-4/+122
| | | | | | | | | Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
* [X86][SSE] Regenerated vec_logical tests.Simon Pilgrim2016-04-011-27/+72
| | | | llvm-svn: 265171
* AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard2016-04-011-0/+89
| | | | | | | | | | | | | | | | | Summary: Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+. 32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý. Patch by: Vedran Miletić Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: jvesely, scchan, kanarayan, arsenm Differential Revision: http://reviews.llvm.org/D17280 llvm-svn: 265170
* [X86][SSE] Regenerated vector sdiv to shifts testsSimon Pilgrim2016-04-011-46/+239
| | | | | | Added SSE + AVX1 tests as well as AVX2 llvm-svn: 265169
* [sancov] save entry block from pruning (it is always full dominator)Mike Aizatsky2016-04-011-3/+2
| | | | llvm-svn: 265168
* [x86] add an SSE1 run for these testsSanjay Patel2016-04-011-105/+106
| | | | | | | | Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
* [X86][SSE] Regenerated vec_setcc tests.Simon Pilgrim2016-04-011-111/+131
| | | | llvm-svn: 265164
* [X86][SSE] Regenerated the vec_set tests.Simon Pilgrim2016-04-0113-128/+214
| | | | | | Replaced lots of dodgy greps with actual codegen llvm-svn: 265163
* [x86] avoid intermediate splat for non-zero memsets (PR27100)Sanjay Patel2016-04-011-18/+10
| | | | | | | | | | | | | | | | | Follow-up to http://reviews.llvm.org/D18566 and http://reviews.llvm.org/D18676 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The 16-byte test that was added in D18566 is now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. Note that the SSE1 path is not changed in this patch. That can be a follow-up. This patch should resolve PR27100. llvm-svn: 265161
* [InstCombine] Don't sink an instr after a catchswitchDavid Majnemer2016-04-011-0/+45
| | | | | | A catchswitch is a terminator, instructions cannot be inserted after it. llvm-svn: 265158
* [SLPVectorizer] Don't insert an extractelement before a catchswitchDavid Majnemer2016-04-011-0/+50
| | | | | | | | | | | | | A catchswitch cannot be preceded by another instruction in the same basic block (other than a PHI node). Instead, insert the extract element right after the materialization of the vectorized value. This isn't optimal but is a reasonable compromise given the constraints of WinEH. This fixes PR27163. llvm-svn: 265157
* [x86] avoid intermediate splat for non-zero memsets (PR27100)Sanjay Patel2016-04-011-113/+66
| | | | | | | | | | | | | | | | | | | | Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
* [PGOProfile] Rename a test to make it more reusable, NFCVedant Kumar2016-04-011-1/+2
| | | | llvm-svn: 265144
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-8/+8
| | | | | | | | $vsrc1 -> $src1, $k -> $imm Differential Revision: http://reviews.llvm.org/D18659 llvm-svn: 265141
* [X86][AVX512] Regenerated intrinsics testsSimon Pilgrim2016-04-011-126/+146
| | | | llvm-svn: 265135
* [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISASagar Thakur2016-04-012-0/+4
| | | | | | | | | | Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 llvm-svn: 265134
* [X86] Introduce Lakemont CPU.Andrey Turetskiy2016-04-011-0/+9
| | | | | | | | Add a new Intel MCU CPU Lakemont, which doesn't support X87. Differential Revision: http://reviews.llvm.org/D18650 llvm-svn: 265128
* Fix for pr24346: arm asm label calculation error in subJames Molloy2016-04-013-0/+36
| | | | | | | | | | | | | | | | | | | | | | Some ARM instructions encode 32-bit immediates as a 8-bit integer (0-255) and a 4-bit rotation (0-30, even) in its least significant 12 bits. The original fixup, FK_Data_4, patches the instruction by the value bit-to-bit, regardless of the encoding. For example, assuming the label L1 and L2 are 0x0 and 0x104 respectively, the following instruction: add r0, r0, #(L2 - L1) ; expects 0x104, i.e., 260 would be assembled to the following, which adds 1 to r0, instead of 260: e2800104 add r0, r0, #4, 2 ; equivalently 1 The new fixup kind fixup_arm_mod_imm takes care of the encoding: e2800f41 add r0, r0, #260 Patch by Ting-Yuan Huang! llvm-svn: 265122
* [AArch64] Better errors for out-of-range fixupsOliver Stannard2016-04-012-1/+65
| | | | | | | | | When a fixup that can be resolved by the assembler is out of range, we should report an error in the source, rather than crashing. Differential Revision: http://reviews.llvm.org/D18402 llvm-svn: 265120
* [OCaml] Reinstate data_layoutJeroen Ketema2016-04-011-0/+1
| | | | | | | | | | | | Expose LLVMCreateTargetMachineData as data_layout. As r263530 did for go. From that commit: "LLVMGetTargetDataLayout was removed from the C API, and then TargetMachine.TargetData was removed. Later, LLVMCreateTargetMachineData was added to the C API" Differential Revision: http://reviews.llvm.org/D18677 llvm-svn: 265115
* Add a module Hash in the bitcode and the combined index, implementing a kind ↵Mehdi Amini2016-04-012-0/+39
| | | | | | | | | | | | | of "build-id" This is intended to be used for ThinLTO incremental build. Differential Revision: http://reviews.llvm.org/D18213 This is a recommit of r265095 after fixing the Windows issues. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265111
* Improve CHECK-NOT robustness of dllexport testsSean Silva2016-04-012-5/+20
| | | | | | | | | | | | | This changes some dllexport tests, to verify that some symbols that should not be exported are not, in a way that improves the robustness of CHECK-SAME interaction with CHECK-NOT. We plan to enable dllimport/dllexport support for the PS4, and these changes are for points we noticed in our internal testing. Patch by Warren Ristow! llvm-svn: 265106
* Revert "Add support for computing SHA1 in LLVM"Mehdi Amini2016-04-012-39/+0
| | | | | | | | This reverts commit r265096, r265095, and r265094. Windows build is broken, and the validation does not pass. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265102
* Don't insert stackrestore on deoptimizing returnsSanjoy Das2016-04-011-0/+16
| | | | | | | | They're not necessary (since the stack pointer is trivially restored on return), and the way LLVM inserts the stackrestore calls breaks the IR (we get a stackrestore between the deoptimize call and the return). llvm-svn: 265101
* Don't insert lifetime end markers on deoptimizing returnsSanjoy Das2016-04-011-0/+16
| | | | | | | | | They're not necessary (since the lifetime of the alloca is trivially over due to the return), and the way LLVM inserts the lifetime.end markers breaks the IR (we get a lifetime end marker between the deoptimize call and the return). llvm-svn: 265100
* Don't use an i64 return type with webkit_jsccSanjoy Das2016-04-011-4/+4
| | | | | | | | | Re-enable an assertion enabled by Justin Lebar in rL265092. rL265092 was breaking test/CodeGen/X86/deopt-intrinsic.ll because webkit_jscc does not like non-i64 return types. Change the test case to not do that. llvm-svn: 265099
* Fix Sub-register Rewriting in Aggressive Anti-Dependence BreakerChuang-Yu Cheng2016-04-011-0/+24
| | | | | | | | | | | | | | | | | | | Previously, HandleLastUse would delete RegRef information for sub-registers if they were dead even if their corresponding super-register were still live. If the super-register were later renamed, then the definitions of the sub-register would not be updated appropriately. This patch alters the behavior so that RegInfo information for sub-registers is only deleted when the sub-register and super-register are both dead. This resolves PR26775. This is the mirror image of Hal's r227311 commit. Author: Tom Jablin (tjablin) Reviewers: kbarton uweigand nemanjai hfinkel http://reviews.llvm.org/D18448 llvm-svn: 265097
* Add missing test for the "Module hash in bitcode" added in r265095Mehdi Amini2016-04-011-0/+4
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265096
* Add a module Hash in the bitcode and the combined index, implementing a kind ↵Mehdi Amini2016-04-011-0/+35
| | | | | | | | | | | of "build-id" This is intended to be used for ThinLTO incremental build. Differential Revision: http://reviews.llvm.org/D18213 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265095
* [NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.Justin Lebar2016-04-011-0/+13
| | | | | | | | | | | | | | | | | | | Summary: Previously the NVVMReflect pass would read its configuration from command-line flags or a static configuration given to the pass at instantiation time. This doesn't quite work for clang's use-case. It needs to pass a value for __CUDA_FTZ down on a per-module basis. We use a module flag for this, so the NVVMReflect pass needs to be updated to read said flag. Reviewers: tra, rnk Subscribers: cfe-commits, jholewinski Differential Revision: http://reviews.llvm.org/D18672 llvm-svn: 265090
* [LoopVectorize] Don't unconditionally print vectorization diagnosticsAkira Hatanaka2016-04-011-2/+50
| | | | | | | | | | | | | | | | | when compiling with LTO. r244523 a new class DiagnosticInfoOptimizationRemarkAnalysisAliasing for optimization analysis remarks related to pointer aliasing without guarding it in isDiagnosticEnabled in LLVMContext.cpp. This caused the diagnostic message to be printed unconditionally when compiling with LTO. This commit cleans up isDiagnosticEnabled and makes sure all the vectorization optimization remarks are guarded. rdar://problem/25382153 llvm-svn: 265084
* testcase gardening: update the emissionKind enum to the new syntax. (NFC)Adrian Prantl2016-04-01479-495/+495
| | | | llvm-svn: 265081
* Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.Adrian Prantl2016-03-31204-216/+232
| | | | | | | | | | | | | This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder into DICompileUnit. DIBuilder is not the right place for this enum to live in — a metadata consumer should not have to include DIBuilder.h. I also added a Verifier check that checks that the emission kind of a DICompileUnit is actually legal. http://reviews.llvm.org/D18612 <rdar://problem/25427165> llvm-svn: 265077
* Create thin archive in GNU format to fix test on OS X.Peter Collingbourne2016-03-311-1/+2
| | | | llvm-svn: 265069
* Move asm-printer-topological-order.ll to PowerPC backendTim Shen2016-03-311-1/+1
| | | | llvm-svn: 265067
* Object: Correctly read thin archives containing absolute paths.Peter Collingbourne2016-03-311-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D18666 llvm-svn: 265065
* [AsmPrinter] Print aliases in topological orderTim Shen2016-03-311-0/+15
| | | | | | | | | | Print aliases in topological order, that is, for any alias a = b, b must be printed before a. This is because on some targets (e.g. PowerPC) linker expects aliases in such an order to generate correct TOC information. GCC also prints aliases in topological order. llvm-svn: 265064
* Preserve blockaddress use edges in the module splitter.Evgeniy Stepanov2016-03-311-0/+37
| | | | | | | | "blockaddress" can not apply to an external function. All blockaddress constant uses must belong to the same module as the definition of the target function. llvm-svn: 265061
* [NVPTX] Infer __nvvm_reflect as nounwind, readnoneDavid Majnemer2016-03-311-0/+5
| | | | | | | | | | This patch simply mirrors the attributes we give to @llvm.nvvm.reflect to the __nvvm_reflect libdevice call. This shaves about 30% of the code in libdevice away because of CSE opportunities. It's also helps us figure out that libdevice implementations of transcendental functions don't have side-effects. llvm-svn: 265060
* [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()Jun Bum Lim2016-03-312-1/+36
| | | | | | | | | | | | | | Summary: This change will allow loads with imp-def to be clustered in machine-scheduler pass. areMemAccessesTriviallyDisjoint() can also handle loads with imp-def. Reviewers: mcrosier, jmolloy, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18665 llvm-svn: 265051
* [PowerPC] Cleanup test/CodeGen/PowerPC/qpx-load-splat.llHal Finkel2016-03-311-14/+6
| | | | | | Removing unnecessary attributes and metadata... llvm-svn: 265049
* [x86] add memset tests to show another potential improvementSanjay Patel2016-03-311-0/+203
| | | | llvm-svn: 265048
* [PowerPC] Add a late MI-level pass for QPX load/splat simplificationHal Finkel2016-03-311-0/+83
| | | | | | | | | | | | | | | Chapter 3 of the QPX manual states that, "Scalar floating-point load instructions, defined in the Power ISA, cause a replication of the source data across all elements of the target register." Thus, if we have a load followed by a QPX splat (from the first lane), the splat is redundant. This adds a late MI-level pass to remove the redundant splats in some of these cases (specifically when both occur in the same basic block). This optimization is scheduled just prior to post-RA scheduling. It can't happen before anything that might replace the load with some already-computed quantity (i.e. store-to-load forwarding). llvm-svn: 265047
* Revert r265039 "[X86] Merge adjacent stack adjustments in ↵Hans Wennborg2016-03-318-46/+18
| | | | | | | | | | eliminateCallFramePseudoInstr (PR27140)" I think it might have caused these build breakages: http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/7234/steps/build%20stage%202/logs/stdio http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19566/steps/run%20tests/logs/stdio llvm-svn: 265046
* [X86][SSE] Some basic tests for variable shufflesSimon Pilgrim2016-03-312-0/+1942
| | | | | | We don't really support non-constant shuffle masks, but these tests are for cases where BUILD_VECTOR is made up from vector extracts (as well as undef/zero scalars). llvm-svn: 265045
* Preserve extern_weak linkage in CloneModule.Evgeniy Stepanov2016-03-311-0/+12
| | | | | | | Only force "extern" linkage if the function used to be a definition in the source module. Declarations keep their original linkage. llvm-svn: 265043
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