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* Added missing test for [ARM] AttributeParser. Check that build attributeAlexandros Lamprineas2015-10-051-0/+7
| | | | | | | | Tag_Advanced_SIMD_arch is set correctly when targeting v8.1-a NEON. Differential Revision: http://reviews.llvm.org/D13281 llvm-svn: 249304
* Fix pr24486.Rafael Espindola2015-10-052-3/+9
| | | | | | | | | | | | | | | | | | This extends the work done in r233995 so that now getFragment (in addition to getSection) also works for variable symbols. With that the existing logic to decide if a-b can be computed works even if a or b are variables. Given that, the expression evaluation can avoid expanding variables as aggressively and that in turn lets the relocation code see the original variable. In order for this to work with the asm streamer, there is now a dummy fragment per section. It is used to assign a section to a symbol when no other fragment exists. This patch is a joint work by Maxim Ostapenko andy myself. llvm-svn: 249303
* Support for function summary index bitcode sections and files.Teresa Johnson2015-10-043-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bitcode format is described in this document: https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view For more info on ThinLTO see: https://sites.google.com/site/llvmthinlto The first customer is ThinLTO, however the data structures are designed and named more generally based on prior feedback. There are a few comments regarding how certain interfaces are used by ThinLTO, and the options added here to gold currently have ThinLTO-specific names as the behavior they provoke is currently ThinLTO-specific. This patch includes support for generating per-module function indexes, the combined index file via the gold plugin, and several tests (more are included with the associated clang patch D11908). Reviewers: dexonsmith, davidxl, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13107 llvm-svn: 249270
* [X86][SSE4A] Added shuffle decode tests for 'special case' SSE4A ↵Simon Pilgrim2015-10-041-0/+61
| | | | | | EXTRQI/INSERTQI ops. llvm-svn: 249263
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-041-0/+183
| | | | llvm-svn: 249262
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-046-0/+968
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* [WinEH] Permit branch folding in the face of funcletsDavid Majnemer2015-10-041-3/+16
| | | | | | | | Track which basic blocks belong to which funclets. Permit branch folding to fire but only if it can prove that doing so will not cause code in one funclet to be reused in another. llvm-svn: 249257
* [DAGCombiner] Generalize FADD constant combines to work with vectorsSimon Pilgrim2015-10-032-24/+49
| | | | | | | | Updated the FADD combines to work with vectors as well as scalars. Differential Revision: http://reviews.llvm.org/D13416 llvm-svn: 249251
* add test cases that demonstrate bad behaviorSanjay Patel2015-10-031-0/+52
| | | | | | | These are based on PR25016 and likely caused by a bug in MachineCombiner's definition of improvesCriticalPathLen(). llvm-svn: 249249
* [llvm-size] Attempt to fix a test failure on Windows.Davide Italiano2015-10-031-1/+1
| | | | llvm-svn: 249247
* [llvm-size] Fix time to check if time of use bug.Davide Italiano2015-10-031-0/+2
| | | | | | This was the last tool relying on this pattern. llvm-svn: 249244
* [X86][SSE] Add FADD combine tests.Simon Pilgrim2015-10-031-0/+196
| | | | llvm-svn: 249240
* [WebAssembly] Implement the remaining conversion operations.Dan Gohman2015-10-031-3/+203
| | | | | | | This is a temporary assembly syntax that will likely evolve along with broader upcoming syntax changes. llvm-svn: 249225
* [WebAssembly] Rename setlocal to set_local to match the spec.Dan Gohman2015-10-0320-303/+303
| | | | llvm-svn: 249218
* [WebAssembly] Update this test for the new loop scheme.Dan Gohman2015-10-021-1/+1
| | | | llvm-svn: 249217
* [SCEV] Recognize simple br-phi patternsSanjoy Das2015-10-021-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Teach SCEV to match patterns like ``` br %cond, label %left, label %right left: br label %merge right: br label %merge merge: V = phi [ %x, %left ], [ %y, %right ] ``` as "select %cond, %x, %y". Before this SCEV would match PHI nodes exclusively to add recurrences. This addresses PR25005. Reviewers: joker.eph, joker-eph, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13378 llvm-svn: 249211
* inariant.group handling in GVNPiotr Padlewski2015-10-022-0/+395
| | | | | | | | | | | | The most important part required to make clang devirtualization works ( ͡°͜ʖ ͡°). The code is able to find non local dependencies, but unfortunatelly because the caller can only handle local dependencies, I had to add some restrictions to look for dependencies only in the same BB. http://reviews.llvm.org/D12992 llvm-svn: 249196
* [WebAssembly] Fix CFG stackification of nested loops.Dan Gohman2015-10-021-0/+30
| | | | llvm-svn: 249187
* [WebAssembly] Support calls marked as "tail", fastcc, and coldcc.Dan Gohman2015-10-021-1/+24
| | | | llvm-svn: 249184
* Call the correct overload.Richard Trieu2015-10-021-3/+3
| | | | | | | Call the correct overload so a string literal does not get converted to a bool. Also fix the test case to match the names given. llvm-svn: 249183
* [WebAssembly] Add a resize_memory intrinsic.Dan Gohman2015-10-022-0/+20
| | | | llvm-svn: 249178
* [Tests] Add one more case to LoopUnroll/pr18861.ll for better coverage.Michael Zolotukhin2015-10-021-0/+31
| | | | llvm-svn: 249174
* [Tests] Give meaningful names to blocks in LoopUnroll/pr18861.ll, add a ↵Michael Zolotukhin2015-10-021-13/+37
| | | | | | description of what's going on. llvm-svn: 249173
* [Tests] Slightly reduce test LoopUnroll/pr18861.ll.Michael Zolotukhin2015-10-021-16/+4
| | | | llvm-svn: 249172
* [WebAssembly] Add a memory_size intrinsic.Dan Gohman2015-10-022-0/+20
| | | | llvm-svn: 249171
* [SCEV] Try to prove predicates by splitting themSanjoy Das2015-10-021-0/+83
| | | | | | | | | | | | | | | | | | | | | Summary: This change teaches SCEV that to prove `A u< B` it is sufficient to prove each of these facts individually: - B >= 0 - A s< B - A >= 0 In practice, SCEV sometimes finds it easier to prove these facts individually than to prove `A u< B` as one atomic step. Reviewers: reames, atrick, nlewycky, hfinkel Subscribers: sanjoy, llvm-commits Differential Revision: http://reviews.llvm.org/D13042 llvm-svn: 249168
* Actually switch the arch when we see .arch. PR21695Roman Divacky2015-10-021-0/+12
| | | | llvm-svn: 249165
* ARM: diagnose invalid local fixups on Thumb1Tim Northover2015-10-027-2/+55
| | | | | | | | | We previously stopped producing Thumb2 relaxations when they weren't supported, but only diagnosed the case where an actual relocation was produced. We should also tell people if local symbols aren't going to work rather than silently overflowing. llvm-svn: 249164
* ARM: correctly align constant pool value on Thumb1 targets.Tim Northover2015-10-021-10/+14
| | | | | | | Since we're using tLDRpci to access it, the constant pool's address must be 0 (mod 4). llvm-svn: 249163
* Reapply r249121 : "[FastISel][x86] Teach how to select SSE2/AVX bitcasts ↵Andrea Di Biagio2015-10-022-0/+489
| | | | | | | | | | | | | | | | | | | | | | | between 128/256-bit vector types." This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Originally reviewed here: http://reviews.llvm.org/D13347 llvm-svn: 249147
* Revert: [FastISel][x86] Teach how to select SSE2/AVX bitcasts between ↵Andrea Di Biagio2015-10-022-489/+0
| | | | | | | | | 128/256-bit vector types. r249121 caused a Clang test failure (avx2-buitins.c). Revert r249121 while I keep investigating on the reason why that test failed. llvm-svn: 249124
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendZoran Jovanovic2015-10-021-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249123
* [FastISel][x86] Teach how to select SSE2/AVX bitcasts between 128/256-bit ↵Andrea Di Biagio2015-10-022-0/+489
| | | | | | | | | | | | | | | | | | | | | | | vector types. This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Differential Revision: http://reviews.llvm.org/D13347 llvm-svn: 249121
* dsymutil: Also ignore the ByteSize when building the DeclContext cache forAdrian Prantl2015-10-024-1/+23
| | | | | | | | clang modules. Forward decls of ObjC interfaces don't have a bytesize. llvm-svn: 249110
* [SimplifyLibCalls] Fix instruction misplacement in string/memory libcall ↵Bruno Cardoso Lopes2015-10-011-0/+26
| | | | | | | | | | | | | | | | | | optimization When trying to optimize fortified library functions use the right location to insert new instructions in order to preserve correct def-use order. This fixes an issue where a misplaced instruction definition would happen to be *after* one of its use after a RAUW, forming invalid IR. This behavior was introduced by r227250. Differential Revision: http://reviews.llvm.org/D13301 rdar://problem/22802369 llvm-svn: 249092
* [Hexagon] XFAILing test while diagnosing backend error.Colin LeMahieu2015-10-011-0/+1
| | | | llvm-svn: 249088
* Fix relocation used for GOT references in non-PIC mode. Fix relocationsJoerg Sonnenberger2015-10-011-11/+33
| | | | | | | | for "set" pseudo op in PIC mode. Differential Revision: http://reviews.llvm.org/D13173 llvm-svn: 249086
* [PATCH] D13360: [llvm-objdump] Teach -d about AArch64 mapping symbolsDavide Italiano2015-10-011-0/+30
| | | | | | | | | | AArch64 uses $d* and $x* to interleave between text and data. llvm-objdump didn't know about this so it ended up printing garbage. This patch is a first step towards a solution of the problem. Differential Revision: http://reviews.llvm.org/D13360 llvm-svn: 249083
* [WinEH] Emit __C_specific_handler tables for the new IRReid Kleckner2015-10-011-0/+202
| | | | | | | | | | | | We emit denormalized tables, where every range of invokes in the same state gets a complete list of EH action entries. This is significantly simpler than trying to infer the correct nested scoping structure from the MI. Fortunately, for SEH, the nesting structure is really just a size optimization. With this, some basic __try / __except examples work. llvm-svn: 249078
* [Hexagon] XFAILing test while diagnosing backend error.Colin LeMahieu2015-10-011-0/+1
| | | | llvm-svn: 249075
* AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering passTom Stellard2015-10-011-0/+24
| | | | | | | | | | | | | | | Summary: Instead of asserting when the kernel metadata is different than we expect, we should just skip lowering that function. This fixes assertion failures with OpenCL argument metadata from older LLVM releases. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13356 llvm-svn: 249073
* [WinEH] Stop BranchFolding from merging across funcletsDavid Majnemer2015-10-011-2/+51
| | | | | | | BranchFolding would merge two funclets together, this is not OK. Disable this and strengthen the assertion in FuncletLayout. llvm-svn: 249069
* [WinEH] Make FuncletLayout more robust against catchretDavid Majnemer2015-10-011-2/+59
| | | | | | | | | Catchret transfers control from a catch funclet to an earlier funclet. However, it is not completely clear which funclet the catchret target is part of. Make this clear by stapling the catchret target's funclet membership onto the CATCHRET SDAG node. llvm-svn: 249052
* [SystemZ] Add some generic (floating point support) load instructions.Jonas Paulsson2015-10-018-14/+95
| | | | | | | | | | | | | | | | | | | | | | Add generic instructions for load complement, load negative and load positive for fp32 and fp64, and let isel prefer them. They do not clobber CC, and so give scheduler more freedom. SystemZElimCompare pass will convert them when it can to the CC-setting variants. Regression tests updated to expect the new opcodes in places where the old ones where used. New test case SystemZ/fp-cmp-05.ll checks that SystemZCompareElim.cpp can handle the new opcodes. README.txt updated (bullet removed). Note that fp128 is not yet handled, because it is relatively rare, and is a bit trickier, because of the fact that l.dfr would operate on the sign bit of one of the subregisters of a fp128, but we would not want to copy the other sub-reg in case src and dst regs are not the same. Reviewed by Ulrich Weigand. llvm-svn: 249046
* Fix printing of 64 bit values and make test more strict.Rafael Espindola2015-10-011-12/+26
| | | | llvm-svn: 249043
* AMDGPU: Add MEM_RAT STORE_TYPED.Tom Stellard2015-10-011-0/+24
| | | | | | | | | | | | v2: Add test (Matt). Fix capitalization of isEOP (Matt). Move pattern to class parameter (Matt). Make the instruction available to Cayman (Matt). Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED. Patch by: Zoltan Gilian llvm-svn: 249042
* Revert r248959, "[WinEH] Emit int3 after noreturn calls on Win64"NAKAMURA Takumi2015-10-013-107/+4
| | | | | | It broke; LLVM :: CodeGen__Generic__2009-11-16-BadKillsCrash.ll llvm-svn: 249032
* [InstCombine] Remove trivially empty lifetime start/end ranges.Arnaud A. de Grandmaison2015-10-011-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some passes may open up opportunities for optimizations, leaving empty lifetime start/end ranges. For example, with the following code: void foo(char *, char *); void bar(int Size, bool flag) { for (int i = 0; i < Size; ++i) { char text[1]; char buff[1]; if (flag) foo(text, buff); // BBFoo } } the loop unswitch pass will create 2 versions of the loop, one with flag==true, and the other one with flag==false, but always leaving the BBFoo basic block, with lifetime ranges covering the scope of the for loop. Simplify CFG will then remove BBFoo in the case where flag==false, but will leave the lifetime markers. This patch teaches InstCombine to remove trivially empty lifetime marker ranges, that is ranges ending right after they were started (ignoring debug info or other lifetime markers in the range). This fixes PR24598: excessive compile time after r234581. Reviewers: reames, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13305 llvm-svn: 249018
* [SystemZ] Add assembly instructions for obtaining clock values as well as ↵Ulrich Weigand2015-10-012-1/+129
| | | | | | | | | | | CPU features Provide assembler support for STCK, STCKF, STCKE, and STFLE. Author: joncmu Differential Revision: http://reviews.llvm.org/D13299 llvm-svn: 249015
* [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructionsZoran Jovanovic2015-10-016-0/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D10337 llvm-svn: 249004
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