summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* Add address space mangling to lifetime intrinsicsMatt Arsenault2017-04-10114-792/+811
| | | | | | In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
* [llvm-pdbdump] Display padding bytes on record layoutZachary Turner2017-04-102-28/+30
| | | | | | | | | | | | | | | When dumping classes, show where padding occurs, and at the end of the class print statistics about how many bytes total of padding exist in a class. Since PDB doesn't specifically contain information about padding, we have to mimic this by sort of reversing a small portion of the record layout algorithm (e.g. looking at offsets and sizes and trying to determine whether something is part of the same field or a new field). Differential Revision: https://reviews.llvm.org/D31800 llvm-svn: 299869
* [MemCpyOpt] Only replace memcpy with bitcast if address spaces matchMatt Arsenault2017-04-101-0/+13
| | | | | | Patch by James Price llvm-svn: 299866
* MemorySSA: Make lifetime starts defs for mustaliased pointersDaniel Berlin2017-04-101-1/+1
| | | | | | | | | | | | | | | | | | Summary: While we don't want them aliasing with other pointers, there seems to be no point in not having them clobber must-aliased'd pointers. If some day, we split the aliasing and ordering chains, we'd make this not aliasing but an ordering barrier (IE it doesn't affect it's memory, but we can't hoist it above it). Reviewers: hfinkel, george.burgess.iv Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31865 llvm-svn: 299865
* [ARM/AArch64] Ensure valid vector element types for interleaved accessesMatthew Simpson2017-04-102-0/+25
| | | | | | | | | | | This patch refactors and strengthens the type checks performed for interleaved accesses. The primary functional change is to ensure that the interleaved accesses have valid element types. The added test cases previously failed because the element type is f128. Differential Revision: https://reviews.llvm.org/D31817 llvm-svn: 299864
* [InstCombine] Use commutable matchers and m_OneUse in visitSub to shorten ↵Craig Topper2017-04-101-0/+122
| | | | | | | | code. Add missing test cases. In one case I removed commute handling for a multiply with a constant since we'll eventually get the constant on the right hand side. llvm-svn: 299863
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+19
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* [InstCombine] Use m_c_Add to shorten some code. Add testcases for this fold ↵Craig Topper2017-04-101-0/+18
| | | | | | since they were missing. NFC llvm-svn: 299853
* [X86][MMX] Add fast-isel support for MMX non-temporal writesSimon Pilgrim2017-04-101-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D31754 llvm-svn: 299852
* [InstCombine] fix matching of or-of-icmps constants (PR32524)Sanjay Patel2017-04-101-4/+3
| | | | | | | | | | | Also, make the same change in and-of-icmps and remove a hack for detecting that case. Finally, add some FIXME comments because the code duplication here is awful. This should fix the remaining IR problem noted in: https://bugs.llvm.org/show_bug.cgi?id=32524 llvm-svn: 299851
* Improves pretty printing of variable types in llvm-pdbdumpAdrian McCarthy2017-04-104-9/+28
| | | | | | | | | | | | | | | | | * Adds support for pointers to arrays, which was missing * Adds some tests * Improves consistency of const and volatile qualifiers * Eliminates non-composable special case code for arrays and function by using a more general recursive approach * Has a hack for getting the calling convention into the right spot for pointer-to-functions Given the rapid changes happenning in llvm-pdbdump, this may be difficult to merge. Differential Revision: https://reviews.llvm.org/D31832 llvm-svn: 299848
* [InstCombine] Support folding of add instructions with vector constants into ↵Craig Topper2017-04-101-6/+3
| | | | | | | | | | select operations We currently only fold scalar add of constants into selects. This improves this to support vectors too. Differential Revision: https://reviews.llvm.org/D31683 llvm-svn: 299847
* [InstCombine] add test for PR32524; NFCSanjay Patel2017-04-101-1/+15
| | | | llvm-svn: 299846
* [ARM] GlobalISel: Support G_FPOW for float and doubleDiana Picus2017-04-102-3/+114
| | | | | | Legalize to a libcall. llvm-svn: 299841
* [InstCombine] Make sure we preserve fast math flags when folding fp ↵Craig Topper2017-04-101-0/+23
| | | | | | | | | | | | | | | | instructions into phi nodes Summary: I noticed in the select folding code that we copied fast math flags, but did not do the same for the similar handling in phi nodes. This patch fixes that to do the same thing as select Reviewers: spatel, davide, majnemer, hfinkel Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31690 llvm-svn: 299838
* [InstCombine] use m_c_And and m_c_Xor to handle commuted versions of a ↵Craig Topper2017-04-101-6/+2
| | | | | | transform. llvm-svn: 299837
* [InstCombine] Add test cases demonstrating missing handling for the commuted ↵Craig Topper2017-04-101-0/+28
| | | | | | version of a transform. NFC. llvm-svn: 299836
* [SCCP] Resolve indirect branch target when possible.Xin Tong2017-04-101-0/+76
| | | | | | | | | | | | | | Summary: Resolve indirect branch target when possible. This potentially eliminates more basicblocks and result in better evaluation for phi and other things. Reviewers: davide, efriedma, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30322 llvm-svn: 299830
* [InstCombine] remove duplicate test; NFCSanjay Patel2017-04-091-12/+0
| | | | | | I moved this test to 'not.ll' in r299824 but accidentally added a copy here. llvm-svn: 299828
* [SimplifyCFG] auto-generate better checks; NFCSanjay Patel2017-04-091-33/+130
| | | | llvm-svn: 299825
* [InstCombine] auto-generate better checks; NFCSanjay Patel2017-04-094-137/+238
| | | | | | Also, move a test next to its sibling to eliminate a file with just one test. llvm-svn: 299824
* [MemorySSA] Fix use of pointsToConstantMemory in ↵Hal Finkel2017-04-091-0/+23
| | | | | | | | | | isUseTriviallyOptimizableToLiveOnEntry In isUseTriviallyOptimizableToLiveOnEntry, pointsToConstantMemory needs to be called on the load's pointer operand, not on the result of the load (which might not even be a pointer). llvm-svn: 299823
* [InstCombine] Extend some OR combines to support vectors.Craig Topper2017-04-091-8/+2
| | | | | | | | This adds support for these combines for vectors (X^C)|Y -> (X|Y)^C iff Y&C == 0 Y|(X^C) -> (X|Y)^C iff Y&C == 0 llvm-svn: 299822
* [InstCombine] Extend a canonicalization check to apply to vector constants too.Craig Topper2017-04-091-4/+4
| | | | llvm-svn: 299821
* [InstCombine] Add test cases to show missing support for vectors in an OR ↵Craig Topper2017-04-091-0/+42
| | | | | | combine. Also add the commuted versions. NFC llvm-svn: 299820
* AMDGPU: Actually write nops for writeNopDataMatt Arsenault2017-04-081-0/+87
| | | | | | | Before this was just writing 0s, which ends up looking like a v_cndmask_b32 v0, s0, v0, vcc. Write out an encoded s_nop instead. llvm-svn: 299816
* [AsmParser]Emit an error if a macro has two (or more) parameters sharing the ↵Coby Tayree2017-04-081-0/+7
| | | | | | | | | | | | | same name Introducing a new error to macro parameters' parsing: currently, llvm-mc won't complain if a macro have two (or more) named params with the same name. this behavior is false, as there's no merit in having some params sharing a name. now, instead of tolerate such a phenomena - emit an appropriate error. Differential Revision: https://reviews.llvm.org/D31674 llvm-svn: 299815
* [coroutines] Make CoroSplit pass deterministicGor Nishanov2017-04-081-6/+4
| | | | | | | | | | | | | | | coro-split-after-phi.ll test was flaky due to non-determinism in the coroutine frame construction that was sorting the spill vector using a pointer to a def as a part of the key. The sorting was intended to make sure that spills for the same def are kept together, however, we populate the vector by processing defs in order, so the spill entires will end up together anyways. This change removes spill sorting and restores the determinism in the test. llvm-svn: 299809
* [ARM] Prefer BIC over BFC in ARM mode.Eli Friedman2017-04-077-19/+25
| | | | | | | | | | | | BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
* [GlobalISel]: Fix bug where we can report GISelFailure on erased instructionsAditya Nandakumar2017-04-071-0/+8
| | | | | | | | | | | | | The original instruction might get legalized and erased and expanded into intermediate instructions and the intermediate instructions might fail legalization. This end up in reporting GISelFailure on the erased instruction. Instead report GISelFailure on the intermediate instruction which failed legalization. Reviewed by: ab llvm-svn: 299802
* [AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18Petr Hosek2017-04-072-0/+28
| | | | | | | | | | | | When using -ffixed-x18, the x18 (or w18) register can safely be used with the "global register variable" GCC extension, but the backend fails to recognize it. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31793 llvm-svn: 299799
* De-flake a test that is failing due to coroutine spill insertion non-determinismReid Kleckner2017-04-071-4/+6
| | | | llvm-svn: 299791
* Revert "[SelectionDAG] Enable target specific vector scalarization of calls ↵Simon Dardis2017-04-074-1697/+24
| | | | | | | | | | | | | and returns" This reverts commit r299766. This change appears to have broken the MIPS buildbots. Reverting while I investigate. Revert "[mips] Remove usage of debug only variable (NFC)" This reverts commit r299769. Follow up commit. llvm-svn: 299788
* [AMDGPU] Unroll more to eliminate phis and conditionsStanislav Mekhanoshin2017-04-071-0/+34
| | | | | | | | | | | | | Increase threshold to unroll a loop which contains an "if" statement whose condition defined by a PHI belonging to the loop. This may help to eliminate if region and potentially even PHI itself, saving on both divergence and registers used for the PHI. Add a small bonus for each of such "if" statements. Differential Revision: https://reviews.llvm.org/D31693 llvm-svn: 299779
* Use PMADDWD to expand reduction in a loopDehao Chen2017-04-071-0/+103
| | | | | | | | | | | | | | | | | | Summary: PMADDWD can help improve 8/16 bit integer mutliply-add operation performance for cases like: for (int i = 0; i < count; i++) a += x[i] * y[i]; Reviewers: wmi, davidxl, hfinkel, RKSimon, zvi, mkuper Reviewed By: mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31679 llvm-svn: 299776
* [GlobalISel] implement narrowing for G_CONSTANT.Igor Breger2017-04-071-0/+43
| | | | | | | | | | | | | | Summary: [GlobalISel] implement narrowing for G_CONSTANT. Reviewers: bogner, zvi, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, dberris, rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D31744 llvm-svn: 299772
* [coroutines] Insert spills of PHI instructions correctlyGor Nishanov2017-04-071-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix a bug where we were inserting a spill in between the PHIs in the beginning of the block. Consider this fragment: ``` begin: %phi1 = phi i32 [ 0, %entry ], [ 2, %alt ] %phi2 = phi i32 [ 1, %entry ], [ 3, %alt ] %sp1 = call i8 @llvm.coro.suspend(token none, i1 false) switch i8 %sp1, label %suspend [i8 0, label %resume i8 1, label %cleanup] resume: call i32 @print(i32 %phi1) ``` Unless we are spilling the argument or result of the invoke, we were always inserting the spill immediately following the instruction. The fix adds a check that if the spilled instruction is a PHI Node, select an appropriate insert point with `getFirstInsertionPt()` that skips all the PHI Nodes and EH pads. Reviewers: majnemer, rnk Reviewed By: rnk Subscribers: qcolombet, EricWF, llvm-commits Differential Revision: https://reviews.llvm.org/D31799 llvm-svn: 299771
* Reapply r298620: [LV] Vectorize GEPsMatthew Simpson2017-04-074-107/+247
| | | | | | | | | | | | | This patch reapplies r298620. The original patch was reverted because of two issues. First, the patch exposed a bug in InstCombine that caused the Chromium builds to fail (PR32414). This issue was fixed in r299017. Second, the patch introduced a bug in the vectorizer's scalars analysis that caused test suite builds to fail on SystemZ. The scalars analysis was too aggressive and marked a memory instruction scalar, even though it was going to be vectorized. This issue has been fixed in the current patch and several new test cases for the scalars analysis have been added. llvm-svn: 299770
* [mips][msa] Fix generation of bm(n)zi and bins[lr]i instructionsPetar Jovanovic2017-04-074-13/+68
| | | | | | | | | | | | | | | | | | | | | | | | | We have two cases here, the first one being the following instruction selection from the builtin function: bm(n)zi builtin -> vselect node -> bins[lr]i machine instruction In case of bm(n)zi having an immediate which has either its high or low bits set, a bins[lr] instruction can be selected through the selectVSplatMask[LR] function. The function counts the number of bits set, and that value is being passed to the bins[lr]i instruction as its immediate, which in turn copies immediate modulo the size of the element in bits plus 1 as per specs, where we get the off-by-one-error. The other case is: bins[lr]i -> vselect node -> bsel.v In this case, a bsel.v instruction gets selected with a mask having one bit less set than required. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D30579 llvm-svn: 299768
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-075-39/+161
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [SelectionDAG] Enable target specific vector scalarization of calls and returnsSimon Dardis2017-04-074-24/+1697
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 299766
* [SystemZ] Check for presence of vector support in SystemZISelLoweringJonas Paulsson2017-04-071-0/+18
| | | | | | | | | | | | | | A test case was found with llvm-stress that caused DAGCombiner to crash when compiling for an older subtarget without vector support. SystemZTargetLowering::combineTruncateExtract() should do nothing for older subtargets. This check was placed in canTreatAsByteVector(), which also helps in a few other places. Review: Ulrich Weigand llvm-svn: 299763
* [ARM] GlobalISel: Test hard float properlyDiana Picus2017-04-071-16/+26
| | | | | | | | It turns out -float-abi=hard doesn't set the hard float calling convention for libcalls. We need to use a hard float triple instead (e.g. gnueabihf). llvm-svn: 299761
* [AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passesSam Kolton2017-04-072-2/+2
| | | | | | | | | | | | | | Summary: Difference beetween PreRegAlloc() and MachineSSAOptimization() are that the former is run despite of -O0 optimization level. In my undestanding SiShrinkInstructions and SDWAPeephole shouldn't run when optimizations are disabled. With this change order of passes will not change. Reviewers: arsenm, vpykhtin, rampitec Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D31705 llvm-svn: 299757
* [ARM] GlobalISel: Support frem for 64-bit valuesDiana Picus2017-04-072-0/+58
| | | | | | Legalize to a libcall. llvm-svn: 299756
* [ARM] GlobalISel: Support frem for 32-bit valuesDiana Picus2017-04-072-0/+48
| | | | | | | | Legalize to a libcall. On this occasion, also start allowing soft float subtargets. For the moment G_FREM is the only legal floating point operation for them. llvm-svn: 299753
* [InstCombine] Handle more commuted cases of ((A & B) | ~A) -> (~A | B)Craig Topper2017-04-071-4/+2
| | | | llvm-svn: 299747
* [InstCombine] Add additional tests with varied commuting to show missing ↵Craig Topper2017-04-071-0/+38
| | | | | | combines. NFC llvm-svn: 299746
* AliasAnalysis: Be less conservative about volatile than atomic.Daniel Berlin2017-04-071-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: getModRefInfo is meant to answer the question "what impact does this instruction have on a given memory location" (not even another instruction). Long debate on this on IRC comes to the conclusion the answer should be "nothing special". That is, a noalias volatile store does not affect a memory location just by being volatile. Note: DSE and GVN and memdep currently believe this, because memdep just goes behind AA's back after it says "modref" right now. see line 635 of memdep. Prior to this patch we would get modref there, then check aliasing, and if it said noalias, we would continue. getModRefInfo *already* has this same AA check, it just wasn't being used because volatile was lumped in with ordering. (I am separately testing whether this code in memdep is now dead except for the invariant load case) Reviewers: jyknight, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31726 llvm-svn: 299741
* [InstCombine] Add more commuted patterns to support folding ((~A & B) | A) ↵Craig Topper2017-04-071-10/+4
| | | | | | -> (A | B). llvm-svn: 299737
OpenPOWER on IntegriCloud