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* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-305-24/+24
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-302-0/+175
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-21/+21
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* [mips] Add support for .cpload.Matheus Almeida2014-04-302-0/+48
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* [mips] Emit all three relocation operations for each relocation entry on ↵Matheus Almeida2014-04-302-0/+4
| | | | | | | | | | | | | | | | Mips64 big-endian systems. Summary: The N64 ABI allows up to three operations to be specified per relocation record independently of the endianness. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3529 llvm-svn: 207636
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-3019-149/+149
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-3011-158/+157
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-3011-51/+51
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [ARM64] Ensure arm64_be is dealt with when emitting debug info.James Molloy2014-04-301-0/+1
| | | | | | | This is a partial port of r204816 (cpirker "Elf support for MC-JIT runtime dynamic linker") from AArch64 to ARM64. llvm-svn: 207625
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-301-8/+34
| | | | llvm-svn: 207620
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-301-0/+24
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. llvm-svn: 207615
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-301-0/+45
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. llvm-svn: 207613
* ARM: partially handle 32-bit relocations for WoASaleem Abdulrasool2014-04-301-0/+27
| | | | | | | | | | | | | | | IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise relocation is not split up and reordered. When expanding the mov32imm pseudo-instruction, create a bundle if the machine operand is referencing an address. This helps ensure that the relocatable address load is not reordered by subsequent passes. Unfortunately, this only partially handles the case as the Constant Island Pass occurs after the instructions are unbundled and does not properly handle bundles. That is a more fundamental issue with the pass itself and beyond the scope of this change. llvm-svn: 207608
* Implement X86 code generation for musttailReid Kleckner2014-04-293-4/+226
| | | | | | | | | | | | | | | | | | Currently, musttail codegen is relying on sibcall optimization, and reporting a fatal error if fails. Sibcall optimization fails when stack arguments need to be modified, which is insufficient for musttail. The logic for moving arguments in memory safely is already implemented for GuaranteedTailCallOpt. This change merely arranges for musttail calls to use it. No functional change for GuaranteedTailCallOpt. Reviewers: espindola Differential Revision: http://reviews.llvm.org/D3493 llvm-svn: 207598
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-2925-25/+25
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-291-0/+27
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-0/+84
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* Also handle ConstantAggregateZero when optimizing vpermilvar*.Rafael Espindola2014-04-291-0/+28
| | | | llvm-svn: 207582
* Two fixes to the vpermilvar optimization.Rafael Espindola2014-04-291-4/+4
| | | | | | | | The instcomine logic to handle vpermilvar's pd and 256 variants was incorrect. The _256 variants have indexes into the individual 128 bit lanes and in all cases it also has to mask out unused bits. llvm-svn: 207577
* Fix vectorization remarks.Diego Novillo2014-04-292-0/+92
| | | | | | | | | This patch changes the vectorization remarks to also inform when vectorization is possible but not beneficial. Added tests to exercise some loop remarks. llvm-svn: 207574
* Continue slp vectorization even the BB already has vectorized store ↵Yi Jiang2014-04-291-0/+31
| | | | | | radar://16641956 llvm-svn: 207572
* Add Simple return instruction to Mips fast-iselReed Kotler2014-04-291-0/+9
| | | | | | | | | | Reviewers: dsanders Reviewed by: dsanders Differential Revision: http://reviews.llvm.org/D3430 llvm-svn: 207565
* [ARM64] Disable regression tests for the old JIT.Tilmann Scheller2014-04-291-3/+4
| | | | | | Since the ARM64 backend doesn't implement support for the old JIT those tests are failing when the regression tests are run on an AArch64 host. llvm-svn: 207530
* [mips][msa] Use CHECK-LABEL in basic_operations*.llDaniel Sanders2014-04-292-42/+42
| | | | | | Differential Revision: http://reviews.llvm.org/D3536 llvm-svn: 207529
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-291-0/+6
| | | | llvm-svn: 207526
* [mips][msa] Fix element extraction where the index is variable.Daniel Sanders2014-04-292-0/+236
| | | | | | | | | | | | | | Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
* Centralize the handling of the thumb bit.Rafael Espindola2014-04-291-0/+15
| | | | | | | | | | | | | This patch centralizes the handling of the thumb bit around MCStreamer::isThumbFunc and makes isThumbFunc handle aliases. This fixes a corner case, but the main advantage is having just one way to check if a MCSymbol is thumb or not. This should still be refactored to be ARM only, but at least now it is just one predicate that has to be refactored instead of 3 (isThumbFunc, ELF_Other_ThumbFunc, and SF_ThumbFunc). llvm-svn: 207522
* ARM: fix test after change to indirect symbol emission.Tim Northover2014-04-291-2/+4
| | | | llvm-svn: 207519
* X86: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-0/+43
| | | | | | rdar://problem/16660411 llvm-svn: 207518
* ARM: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-0/+22
| | | | | | rdar://problem/16660411 llvm-svn: 207517
* AArch64: Mark vector long multiplication as expand.Benjamin Kramer2014-04-291-0/+14
| | | | | | | There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. llvm-svn: 207515
* AVX-512: optimized a shuffle pattern to VINSERTI64x4.Elena Demikhovsky2014-04-292-1/+28
| | | | | | Added intrinsics for VPERMT2PS/PD/D/Q instructions. llvm-svn: 207513
* [OPENMP][LV][D3423] Respect Hints.Force meta-data for loops in LoopVectorizerZinovy Nis2014-04-292-0/+166
| | | | llvm-svn: 207512
* [ARM64]Fix a bug about incorrect operand order in an EXT instruction, which ↵Hao Liu2014-04-291-0/+23
| | | | | | is introduced by r207485. llvm-svn: 207500
* [ARM64]Fix a bug when lowering shuffle vector to an EXT instruction.Hao Liu2014-04-291-0/+17
| | | | | | E.g. Mask like <-1, -1, 1, ...> will generate incorrect EXT index. llvm-svn: 207485
* Revert r207271 for now. This commit introduced a test case that ranChandler Carruth2014-04-282-37/+1
| | | | | | | | clang directly from the LLVM test suite! That doesn't work. I've followed up on the review thread to try and get a viable solution sorted out, but trying to get the tree clean here. llvm-svn: 207462
* Add an option for evaluating past symbols.Rafael Espindola2014-04-281-0/+59
| | | | | | | | | | | | | When evaluating an assembly expression for a relocation, we want to stop at MCSymbols that are in the symbol table, even if they are variables. This is needed since the semantics may require that the relocation use them. That is not the case when computing the value of a symbol in the symbol table. There are no relocations in this case and we have to keep going until we hit a section or find out that the expression doesn't have an assembly time value. llvm-svn: 207445
* DwarfDebug: Omit DW_AT_object_pointer on inlined_subroutinesDavid Blaikie2014-04-281-0/+90
| | | | | | | | | | | | | | | | While refactoring out constructScopeDIE into two functions I realized we were emitting DW_AT_object_pointer in the inlined subroutine when we didn't need to (GCC doesn't, and the abstract subprogram definition has the information already). So here's the refactoring and the bug fix. This is one step of refactoring to remove some subtle memory ownership semantics. It turns out the original constructScopeDIE returned ownership in its return value in some cases and not in others. The split into two functions now separates those two semantics - further cleanup (unique_ptr, etc) will follow. llvm-svn: 207441
* Reapply "blockfreq: Approximate irreducible control flow"Duncan P. N. Exon Smith2014-04-281-56/+281
| | | | | | | | | | This reverts commit r207287, reapplying r207286. I'm hoping that declaring an explicit struct and instantiating `addBlockEdges()` directly works around the GCC crash from r207286. This is a lot more boilerplate, though. llvm-svn: 207438
* InstCombine: don't drop 'inalloca' in PromoteCastOfAllocation (PR19569)Hans Wennborg2014-04-281-0/+21
| | | | llvm-svn: 207426
* [ARM64] Fix an issue where we were always assuming a copy was coming from a ↵Chad Rosier2014-04-281-1/+30
| | | | | | D subregister. llvm-svn: 207423
* Don't include an invalid symbol in the symbol table.Rafael Espindola2014-04-281-0/+3
| | | | | | | | | | | | The symbol table itself has no relocations, so it is not possible to represent things like a = undefined + 1 With the patch we just omit these variables. That matches the behaviour of the gnu assembler. llvm-svn: 207419
* List the entire symbol table in this test.Rafael Espindola2014-04-281-10/+66
| | | | | | | This will allow us to extend this test to show that other symbols don't show up in the symbol table. llvm-svn: 207418
* Produce an error instead of a crash in an expr we cannot represent.Rafael Espindola2014-04-281-0/+8
| | | | llvm-svn: 207414
* ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.Tim Northover2014-04-281-0/+11
| | | | | | | | | | | Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
* [inliner] Significantly improve the compile time in cases like PR19499Chandler Carruth2014-04-281-0/+60
| | | | | | | | | | | | | | | by avoiding inlining massive switches merely because they have no instructions in them. These switches still show up where we fail to form lookup tables, and in those cases they are actually going to cause a very significant code size hit anyways, so inlining them is not the right call. The right way to fix any performance regressions stemming from this is to enhance the switch-to-lookup-table logic to fire in more places. This makes PR19499 about 5x less bad. It uncovers a second compile time problem in that test case that is unrelated (surprisingly!). llvm-svn: 207403
* [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.Hao Liu2014-04-281-0/+19
| | | | llvm-svn: 207399
* Update tests to use the new format of printing a TimeValue. It's a bitChandler Carruth2014-04-282-13/+13
| | | | | | | | | | | | odd to have the output of 'llvm-ar tv' depend on the format of TimeValue::str(), but that's what we have today. If anyone needs the output to remain compatible with GNU ar or old versions of llvm-ar, just shout and I'll switch the code to manually format its times. Note that there isn't a portable format -- Mac and GNU have different formats at least (thanks Rafael!) so... llvm-svn: 207387
* Add emitThumbSet to the arm target streamer.Rafael Espindola2014-04-271-0/+5
| | | | | | | This fixes the asm printer implementation and lets the parser be unaware of what .thumb_set is. llvm-svn: 207381
* X86TTI: Adjust sdiv cost now that we can lower it on plain SSE2.Benjamin Kramer2014-04-271-2/+2
| | | | | | | Includes a fix for a horrible typo that caused all SDIV costs to be slightly off :) llvm-svn: 207371
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