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* ELFYAML: Add support for parsing AMDGPU section attribute flagsTom Stellard2015-11-131-1/+16
| | | | | | | | | | Reviewers: silvas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14444 llvm-svn: 253052
* [ARM] Replace ARMISD::RBIT with ISD::BITREVERSEJames Molloy2015-11-131-0/+11
| | | | | | ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering. llvm-svn: 253047
* [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, ↵Zlatko Buljan2015-11-138-0/+84
| | | | | | | | SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
* [mips][ias] Explicitly disable IAS on asm-large-immediate.ll.Daniel Sanders2015-11-131-1/+2
| | | | | | NFC at the moment but it will prevent a failure when IAS is enabled by default. llvm-svn: 253039
* [mips][ias] Replace invalid assembly insn in test since IAS parses inline ↵Daniel Sanders2015-11-131-2/+2
| | | | | | | | | assembly. This is NFC at the moment but will prevent this test from failing when IAS is the default. llvm-svn: 253033
* [AArch64] Check the expansion of BITREVERSE in regression testJames Molloy2015-11-131-2/+21
| | | | | | | | Something I missed from Hal's review, rightly pointed out by Ben Kramer - we should make sure the expansion is properly checked as it can be easy for bugs to creep in. I've checked the scalar i8 expansion here and the vector i8 expansion in a previous commit. llvm-svn: 253024
* [SDAG] Fix expansion of BITREVERSEJames Molloy2015-11-131-0/+45
| | | | | | | | | | Richard Trieu noted that UBSan detected an overflowing shift, and the obvious fix caused a crash. What was happening was that the shiftee (1U) was indeed too small for the possible range of shifts it had to handle, but also we were using "VT.getSizeInBits()" to get the maximum type bitwidth, but we wanted "VT.getScalarSizeInBits()" to get the vector lane size instead of the entire vector size. Use an APInt for the shift and VT.getScalarSizeInBits(). llvm-svn: 253023
* llvm/test/tools/llvm-profdata/text-format-errors.test: Use prepared version ↵NAKAMURA Takumi2015-11-132-2/+2
| | | | | | | | of the input file, instead of using echo. ...and s/\C9/\xC9/ llvm-svn: 253014
* [llvm-profdata] Add check for text profile formats and improve error ↵Nathan Slingerland2015-11-134-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reporting (2nd try) Summary: This change addresses two possible instances of user error / confusion when merging sampled profile data. Previously any input that didn't match the raw or processed instrumented format would automatically be interpreted as instrumented profile text format data. No error would be reported during the merge. Example: If foo-sampled.profdata and bar-sampled.profdata are binary sampled profiles: Old behavior: $ llvm-profdata merge foo-sampled.profdata bar-sampled.profdata -output foobar-sampled.profdata $ llvm-profdata show -sample foobar-sampled.profdata error: foobar-sampled.profdata:1: Expected 'mangled_name:NUM:NUM', found lprofi This change adds basic checks for valid input data when assuming text input. It also makes error messages related to file format validity more specific about the assumbed profile data type. New behavior: $ llvm-profdata merge foo-sampled.profdata bar-sampled.profdata -o foobar-sampled.profdata error: foo.profdata: Unrecognized instrumentation profile encoding format Perhaps you forgot to use the -sample option? Reviewers: bogner, davidxl, dnovillo Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D14558 llvm-svn: 253009
* [Hexagon] NFC. Adding a number of packet correctness tests.Colin LeMahieu2015-11-135-0/+88
| | | | llvm-svn: 253000
* [WebAssembly] Inline asm support.Dan Gohman2015-11-131-0/+53
| | | | llvm-svn: 252997
* [Hexagon] Adding relaxation functionality to backend and test.Colin LeMahieu2015-11-132-0/+25
| | | | llvm-svn: 252989
* [WinEH] Find root frame correctly in CLR funcletsJoseph Tremoulet2015-11-131-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The value that the CoreCLR personality passes to a funclet for the establisher frame may be the root function's frame or may be the parent funclet's (mostly empty) frame in the case of nested funclets. Each funclet stores a pointer to the root frame in its own (mostly empty) frame, as does the root function itself. All frames allocate this slot at the same offset, measured from the post-prolog stack pointer, so that the same sequence can accept any ancestor as an establisher frame parameter value, and so that a single offset can be reported to the GC, which also looks at this slot. This change allocate the slot when processing function entry, and records its frame index on the WinEHFuncInfo object, then inserts the code to set/copy it during prolog emission. Reviewers: majnemer, AndyAyers, pgavlin, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14614 llvm-svn: 252983
* [WebAssembly] Introduce a new pseudo-operand for unused expression results.Dan Gohman2015-11-131-0/+9
| | | | llvm-svn: 252975
* X86-FMA3: Implemented commute transformations FMA*_Int instructions.Vyacheslav Klochkov2015-11-132-48/+303
| | | | | | | | | | It made it possible to apply the memory folding optimization for the 2nd operand of FMA*_Int instructions. Reviewer: Quentin Colombet Differential Revision: http://reviews.llvm.org/D14550 llvm-svn: 252973
* [Hexagon] Adding checks for values out of operand range and correct ↵Colin LeMahieu2015-11-122-0/+82
| | | | | | new-value producer usage. llvm-svn: 252969
* [Hexagon] Adding test to make sure labels and register pairs are correctly ↵Colin LeMahieu2015-11-121-0/+26
| | | | | | parsed. llvm-svn: 252968
* specify triple and tighten checks using update_llc_test_checks.pySanjay Patel2015-11-121-61/+62
| | | | llvm-svn: 252962
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-122-3/+3
| | | | | | | | | | | | | This reverts commit r252565. This also includes the revert of the commit mentioned below in order to avoid breaking tests in AMDGPU: Revert "AMDGPU: Set isAllocatable = 0 on VS_32/VS_64" This reverts commit r252674. llvm-svn: 252956
* disabling sancov tests: too many failures on different platforms.Mike Aizatsky2015-11-122-0/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D14624 llvm-svn: 252945
* sancov tests - platform independent separatorsMike Aizatsky2015-11-121-4/+4
| | | | llvm-svn: 252943
* Revert "Fix bug 25440: GVN assertion after coercing loads"Tobias Grosser2015-11-121-66/+0
| | | | | | This reverts 252919 which broke LNT: MultiSource/Applications/SPASS llvm-svn: 252936
* sancov test suiteMike Aizatsky2015-11-128-7/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D14589 llvm-svn: 252933
* [ThinLTO] Update test to be more tolerant of ordering changesTeresa Johnson2015-11-121-40/+40
| | | | | | | | | Update the ThinLTO function importing test to use DAG forms of checks so that it is more tolerant of changes to relative ordering between imported decls/defs. This reduces the number of changes required by the comdat importing patch I am sending for review shortly. llvm-svn: 252932
* reverting r252916 to investigate test failureNathan Slingerland2015-11-123-19/+4
| | | | llvm-svn: 252921
* Fix bug 25440: GVN assertion after coercing loadsWeiming Zhao2015-11-121-0/+66
| | | | | | | | | | | | | | | | Summary: when coercing loads, it inserts some instructions, which have no GV assigned. https://llvm.org/bugs/show_bug.cgi?id=25440 Reviewers: hfinkel, dberlin Subscribers: dberlin, llvm-commits Differential Revision: http://reviews.llvm.org/D14479 llvm-svn: 252919
* [ShrinkWrap] Make sure we do not mess up with EH funclet lowering.Quentin Colombet2015-11-121-1/+3
| | | | | | | | ShrinkWrapping does not understand exception handling constraints for now, so make sure we do not mess with them by aborting on functions that use EH funclets. llvm-svn: 252917
* [llvm-profdata] Add check for text profile formats and improve error reportingNathan Slingerland2015-11-123-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change addresses two possible instances of user error / confusion when merging sampled profile data. Previously any input that didn't match the raw or processed instrumented format would automatically be interpreted as instrumented profile text format data. No error would be reported during the merge. Example: If foo-sampled.profdata and bar-sampled.profdata are binary sampled profiles: Old behavior: $ llvm-profdata merge foo-sampled.profdata bar-sampled.profdata -output foobar-sampled.profdata $ llvm-profdata show -sample foobar-sampled.profdata error: foobar-sampled.profdata:1: Expected 'mangled_name:NUM:NUM', found lprofi This change adds basic checks for valid input data when assuming text input. It also makes error messages related to file format validity more specific about the assumbed profile data type. New behavior: $ llvm-profdata merge foo-sampled.profdata bar-sampled.profdata -o foobar-sampled.profdata error: foo.profdata: Unrecognized instrumentation profile encoding format Perhaps you forgot to use the -sample option? Reviewers: bogner, davidxl, dnovillo Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D14558 llvm-svn: 252916
* [WebAssembly] Reapply r252858, with svn add for the new file.Dan Gohman2015-11-1229-901/+623
| | | | | | | | | | | | | | | | | | | | | | Switch to MC for instruction printing. This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing does not use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252910
* [x86] translating "fp" (floating point) instructions from ↵Michael Zuckerman2015-11-122-0/+28
| | | | | | | | | | | {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp} LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr. GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions. Differential Revision: http://reviews.llvm.org/D14217 llvm-svn: 252908
* Revert r252858: "[WebAssembly] Switch to MC for instruction printing."Hans Wennborg2015-11-1229-623/+901
| | | | | | | | It broke the CMake build: "Cannot find source file: WebAssemblyRegNumbering.cpp" llvm-svn: 252897
* Re-apply "[mips] Use correct frame register for DWARF info when dynamically ↵Vasileios Kalintiris2015-11-122-0/+281
| | | | | | | | | realigning the stack."" r252219 reversed the direction of subprogram -> function edge. Fixed the IR to account for this. llvm-svn: 252895
* [ARM] CMOV->BFI combining: handle both senses of CMPZJames Molloy2015-11-121-0/+11
| | | | | | | | I completely misunderstood what ARMISD::CMPZ means. It's not "compare equal to zero", it's "compare, only setting the zero/Z flag". It can either be equal-to-zero or not-equal-to-zero, and we weren't checking what sense it was. If it's equal-to-zero, we can swap the operands around and pretend like it is not-equal-to-zero, which is both a bug fix and lets us handle more cases. llvm-svn: 252891
* Revert "[ARM] Enable shrink-wrapping by default."Renato Golin2015-11-1211-27/+18
| | | | | | This reverts commit r252825, as it broke ASAN on ARM. Investigating... llvm-svn: 252889
* Implement .reloc (constant offset only) with support for R_MIPS_NONE and ↵Daniel Sanders2015-11-122-0/+64
| | | | | | | | | | | | | | | | R_MIPS_32. Summary: Support for R_MIPS_NONE allows us to parse MIPS16's usage of .reloc. R_MIPS_32 was included to be able to better test the directive. Targets can add their relocations by overriding MCAsmBackend::getFixupKind(). Subscribers: grosbach, rafael, majnemer, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13659 llvm-svn: 252888
* [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructionsZlatko Buljan2015-11-126-0/+88
| | | | | | Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
* Revert "[mips] Use correct frame register for DWARF info when dynamically ↵Vasileios Kalintiris2015-11-122-281/+0
| | | | | | | | | realigning the stack." This reverts commit r252882. LLParser complains for invalid field 'function' in DISubprogram. llvm-svn: 252884
* [mips] Use correct frame register for DWARF info when dynamically realigning ↵Vasileios Kalintiris2015-11-122-0/+281
| | | | | | | | | | | | | | | | | | | the stack. Summary: This patch overrides TargetFrameLowering::getFrameIndexReference() in order to specify the correct register when the function needs dynamic stack realignment. The values returned from this function are used in order to create DW_AT_locations for DWARF info. These locations would use the wrong registers as it's been reported in PR25028. Reviewers: dsanders Subscribers: dean, llvm-commits Differential Revision: http://reviews.llvm.org/D13511 llvm-svn: 252882
* [InstCombine] Add trivial folding (bitreverse (bitreverse x)) -> xJames Molloy2015-11-121-0/+11
| | | | | | There are plenty more instcombines we could probably do with bitreverse, but this seems like a very obvious and trivial starting point and was brought up by Hal in his review. llvm-svn: 252879
* [SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsicJames Molloy2015-11-123-0/+68
| | | | | | | | | | Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
* Revert "Revert "[FunctionAttrs] Identify norecurse functions""James Molloy2015-11-126-10/+74
| | | | | | This reapplies this patch, with test fixes. llvm-svn: 252871
* [Object, MachO] Mark symbols from DATA and BSS sections as ST_DataKuba Brecka2015-11-121-3/+3
| | | | | | | | In `MachOObjectFile::getSymbolType` we currently always return `SymbolRef::ST_Function` for symbols from any section. In order for llvm-symbolizer to correctly symbolize Mach-O globals, symbols from data and BSS sections should return `SymbolRef::ST_Data`. Differential Revision: http://reviews.llvm.org/D14576 llvm-svn: 252867
* dwarfdump: Added macro support to llvm-dwarfdump tool.Amjad Aboud2015-11-125-0/+44
| | | | | | | | Added "macro" option to "-debug-dump" flag, which trigger parsing and dumping of the ".debug_macinfo" section. Differential Revision: http://reviews.llvm.org/D14294 llvm-svn: 252866
* Revert "[FunctionAttrs] Identify norecurse functions"James Molloy2015-11-126-74/+10
| | | | | | This reverts commit r252862. This introduced test failures and I'm reverting while I investigate how this happened. llvm-svn: 252863
* [FunctionAttrs] Identify norecurse functionsJames Molloy2015-11-126-10/+74
| | | | | | | | | | | | | A function can be marked as norecurse if: * The SCC to which it belongs has cardinality 1; and either a) It does not call any non-norecurse function. This includes self-recursion; or b) It only has one callsite and the function that callsite is within is marked norecurse. a) is best propagated bottom-up and b) is best propagated top-down. We build up the norecurse attributes bottom-up using the existing SCC pass, and mark functions with no obvious recursion (but not provably norecurse) to sweep later, top-down. llvm-svn: 252862
* Mostly revert 252842 due to failures on some buildbots.David Blaikie2015-11-121-10/+10
| | | | | | | | | | | | | | I imagine there's some UB in here somewhere, though Valgrind doesn't seem to have picked it up (not sure if I have a working asan build right now to test there). GDB bot seems to be crashing: http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/26267/steps/check-all/logs/FAIL%3A%20LLVM%3A%3Adwarfdump-dwp.test Hexagon ELF bot is, presumably, just getting different output: http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/32927/steps/check-all/logs/FAIL%3A%20LLVM%3A%3Adwarfdump-dwp.test llvm-svn: 252859
* [WebAssembly] Switch to MC for instruction printing.Dan Gohman2015-11-1229-901/+623
| | | | | | | | | | | | | | | | | | | | This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252858
* dwarfdump: Dump the contents of DWP indexesDavid Blaikie2015-11-122-13/+12
| | | | llvm-svn: 252842
* LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalizationMatthias Braun2015-11-122-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Factor out code to query and modify the sign bit of a floatingpoint value as an integer. This also works if none of the targets integer types is big enough to hold all bits of the floatingpoint value. - Legalize FABS(x) as FCOPYSIGN(x, 0.0) if FCOPYSIGN is available, otherwise perform bit manipulation on the sign bit. The previous code used "x >u 0 ? x : -x" which is incorrect for x being -0.0! It also takes 34 instructions on ARM Cortex-M4. With this patch we only require 5: vldr d0, LCPI0_0 vmov r2, r3, d0 lsrs r2, r3, #31 bfi r1, r2, #31, #1 bx lr (This could be further improved if the compiler would recognize that r2, r3 is zero). - Only lower FCOPYSIGN(x, y) = sign(x) ? -FABS(x) : FABS(x) if FABS is available otherwise perform bit manipulation on the sign bit. - Perform the sign(x) test by masking out the sign bit and comparing with 0 rather than shifting the sign bit to the highest position and testing for "<s 0". For x86 copysignl (on 80bit values) this gets us: testl $32768, %eax rather than: shlq $48, %rax sets %al testb %al, %al Differential Revision: http://reviews.llvm.org/D11172 llvm-svn: 252839
* [TLS on Darwin] use a different mask for tls calls on x86-64.Manman Ren2015-11-121-0/+28
| | | | | | | | | Calls involved in thread-local variable lookup save more registers than normal calls. rdar://problem/23073171 llvm-svn: 252837
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