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* [llvm-readobj] Print MIPS PLT tableSimon Atanasyan2015-07-092-0/+34
| | | | | | Now the -mips-plt-got prints both MIPS GOT and PLT tables. llvm-svn: 241836
* [yaml2obj] Initialize sh_addralign field for the .symtab sectionSimon Atanasyan2015-07-091-0/+3
| | | | llvm-svn: 241835
* [ELF] Explicitly configure sections alignment in the tests. NFCSimon Atanasyan2015-07-092-0/+2
| | | | llvm-svn: 241834
* [llvm-objdump] Require that jump targets shown in -d are functionsDavid Majnemer2015-07-091-0/+4
| | | | | | | Don't let the disassembler pick call <.text> if a function happens to live at the start of the section by only using function symbols. llvm-svn: 241830
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-092-0/+42
| | | | | | | | | | This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
* fix an invisible bug when combining repeated FP divisorsSanjay Patel2015-07-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG: r237046 ( http://reviews.llvm.org/rL237046 ): 1. When replacing a division node, it's not enough to RAUW. We should call CombineTo() to delete dead nodes and combine again. 2. Because we are changing the DAG, we can't return an empty SDValue after the transform. As the code comments say: Visitation implementation - Implement dag node combining for different node types. The semantics are as follows: Return Value: SDValue.getNode() == 0 - No change was made SDValue.getNode() == N - N was replaced, is dead and has been handled. otherwise - N should be replaced by the returned Operand. The new test case shows no difference with or without this patch, but it will crash if we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt. Differential Revision: http://reviews.llvm.org/D9893 llvm-svn: 241826
* Add a test of a regression discovered during testing of r241673Silviu Baranga2015-07-091-0/+64
| | | | | | | | | | | | | | | Summary: We were missing a corner case where DepCands was not available, but we were using DepCands to compute the checking pointer groups. This adds a test for that regression. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11068 llvm-svn: 241818
* Add missing file from previous commit.Rafael Espindola2015-07-091-0/+0
| | | | llvm-svn: 241815
* Basic support for BSD symbol tables in archives.Rafael Espindola2015-07-091-0/+21
| | | | | | | This could be optimized and for now we only produce __.SYMDEF and not "__.SYMDEF SORTED". llvm-svn: 241814
* Don't rely on the DepCands iteration order when constructing checking ↵Silviu Baranga2015-07-092-30/+30
| | | | | | | | | | | | | | | | | | | pointer groups Summary: The checking pointer group construction algorithm relied on the iteration on DepCands. We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism. This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic. We need to update the tests, since the order in which pointers appear has changed. No new tests were added, since it is impossible to test for non-determinism. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11064 llvm-svn: 241809
* Reapply fixed r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-0/+44
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-091-0/+71
| | | | llvm-svn: 241804
* [AArch64] Select SBFIZ or UBFIZ instead of left + right shiftsArnaud A. de Grandmaison2015-07-091-0/+33
| | | | | | And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology. llvm-svn: 241803
* [ARM] Thumb1 3 to 2 operand convertion for commutative operationsScott Douglass2015-07-092-0/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D11057 llvm-svn: 241802
* [ARM] Don't be overzealous converting Thumb1 3 to 2 operandsScott Douglass2015-07-091-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11056 llvm-svn: 241801
* [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2Scott Douglass2015-07-091-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11055 llvm-svn: 241800
* [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)Scott Douglass2015-07-091-0/+19
| | | | | | | | Also adds some test cases. Differential Revision: http://reviews.llvm.org/D11054 llvm-svn: 241799
* [ARM] Add ADD tests for Thumb2 narrowing (nfc)Scott Douglass2015-07-091-1/+67
| | | | | | Differential Revision: http://reviews.llvm.org/D11053 llvm-svn: 241798
* Test for 241794 (nest attribute in AArch64)Renato Golin2015-07-091-0/+23
| | | | | | | | Forgot to git add the test. Patch by Stephen Cross. llvm-svn: 241797
* Revert r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-44/+0
| | | | llvm-svn: 241792
* Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-0/+44
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241790
* Extended syntax of vector version of getelementptr instruction.Elena Demikhovsky2015-07-094-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements. %A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value. (1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets or (2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset In all cases the %A type is <4 x i8*> In the case (2) we add the same offset to all pointers. The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i]. The documentation is updated. http://reviews.llvm.org/D10496 llvm-svn: 241788
* Temporarily reverting 241765, 241768, and 241772 to unbreak the build bots.Adrian Prantl2015-07-092-8/+0
| | | | llvm-svn: 241781
* [Object][ELF] Support dumping hash-tables from files with no section table.Michael J. Spencer2015-07-092-0/+8
| | | | llvm-svn: 241765
* [CodeView] Add support for emitting column informationDavid Majnemer2015-07-095-34/+216
| | | | | | | | | | Column information is present in CodeView when the line table subsection has bit 0 set to 1 in it's flags field. The column information is represented as a pair of 16-bit quantities: a starting and ending column. This information is present at the end of the chunk, after all the line-PC pairs. llvm-svn: 241764
* MIR Serialization: Serialize the 'undef' register machine operand flag.Alex Lorenz2015-07-081-0/+42
| | | | llvm-svn: 241762
* [SLPVectorizer] Try different vectorization factors for store chainsSanjay Patel2015-07-085-24/+39
| | | | | | | | | | | | | | | | ...and set max vector register size based on target This patch is based on discussion on the llvmdev mailing list: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-July/087405.html and also solves: https://llvm.org/bugs/show_bug.cgi?id=17170 Several FIXME/TODO items are noted in comments as potential improvements. Differential Revision: http://reviews.llvm.org/D10950 llvm-svn: 241760
* [LAA] Revert a small part of r239295Adam Nemet2015-07-081-0/+42
| | | | | | | | | | | | | | | | This commit ([LAA] Fix estimation of number of memchecks) regressed the logic a bit. We shouldn't quit the analysis if we encounter a pointer without known bounds *unless* we actually need to emit a memcheck for it. The original code was using NumComparisons which is now computed differently. Instead I compute NeedRTCheck from NumReadPtrChecks and NumWritePtrChecks. As side note, I find the separation of NeedRTCheck and CanDoRT confusing, so I will try to merge them in a follow-up patch. llvm-svn: 241756
* [x86] enable machine combiner reassociations for scalar single-precision ↵Sanjay Patel2015-07-083-6/+27
| | | | | | multiplies llvm-svn: 241752
* Don't reject an archive with just a symbol table.Rafael Espindola2015-07-082-0/+4
| | | | | | It is pretty unambiguous how to interpret it and gnu ar accepts it too. llvm-svn: 241750
* Add tests for the NVPTXLowerAggrCopies pass.Eli Bendersky2015-07-081-0/+34
| | | | | | | Note: not testing memmove lowering for now, as it's broken [see https://llvm.org/bugs/show_bug.cgi?id=24056] llvm-svn: 241736
* MIR Serialization: Serialize the 'killed' register machine operand flag.Alex Lorenz2015-07-081-0/+42
| | | | llvm-svn: 241734
* [X86][SSE] Vector shift test cleanup. NFC.Simon Pilgrim2015-07-086-1280/+1280
| | | | llvm-svn: 241730
* [Win64] Only treat some functions as having the Win64 conventionReid Kleckner2015-07-081-0/+18
| | | | | | | | | | | | | | | | All the usual X86 target-specific conventions are collapsed to the normal Win64 convention, but the custom conventions like GHC and webkit should not be. Previously we would assume that the caller allocated 32 bytes of shadow space for us, which is not how webkit_jscc or other custom conventions are supposed to work. Based on a patch by peavo@outlook.com. Fixes PR24051. llvm-svn: 241725
* Start adding support for writing archives in BSD format.Rafael Espindola2015-07-081-0/+10
| | | | | | | | No support for the symbol table yet (but will hopefully add it today). We always use the long filename format so that we can align the member, which is an advantage of the BSD format. llvm-svn: 241721
* MIR Parser: Use source locations for MBB naming errors.Alex Lorenz2015-07-081-1/+1
| | | | | | | | | This commit changes the type of the field 'Name' in the struct 'yaml::MachineBasicBlock' from 'std::string' to 'yaml::StringValue'. This change allows the MIR parser to report errors related to the MBB name with the proper source locations. llvm-svn: 241718
* [Hexagon] Implement commoning of GetElementPtr instructionsKrzysztof Parzyszek2015-07-082-0/+113
| | | | llvm-svn: 241714
* LibDriver: Fix output path inference.Peter Collingbourne2015-07-081-0/+15
| | | | | | | | | The inferred output file name is based on the first input file, not the first one with extension .obj. The output file was also being written to the wrong directory; it needs to be written to whichever directory on the libpath it was found in. This change fixes both issues. llvm-svn: 241710
* [SEH] Add missing test case from previous realignment commitReid Kleckner2015-07-081-0/+101
| | | | llvm-svn: 241700
* [SEH] Ensure that empty __except blocks have their own BBReid Kleckner2015-07-081-0/+32
| | | | | | | | | The 32-bit lowering assumed that WinEHPrepare had this invariant. WinEHPrepare did it for C++, but not SEH. The result was that we would insert calls to llvm.x86.seh.restoreframe in normal basic blocks, which corrupted the frame pointer. llvm-svn: 241699
* [SPARC] Cleanup handling of the Y/ASR registers.James Y Knight2015-07-082-1/+22
| | | | | | | | | | | | | | | | | | - Implement copying ASR to/from GPR regs. - Mark ASRs as non-allocatable, so it won't try to arbitrarily use them inappropriately. - Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV routines, just do normal register copies. - Also...mark div as using Y, not just writing it. Added a test case with some code which previously died with an assertion failure (with -O0), or produced wrong code (otherwise). (Third time's the charm?) Differential Revision: http://reviews.llvm.org/D10401 llvm-svn: 241686
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241683
* Revert 241681: causes Windows builds to failKrzysztof Parzyszek2015-07-081-66/+0
| | | | llvm-svn: 241682
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241681
* [yaml2obj] Align section content using AddressAlign field's valueSimon Atanasyan2015-07-081-0/+53
| | | | | | | | Use AddressAlign field's value to properly align sections content in the yaml2obj tool. Before this change the yaml2obj ignored AddressAlign and always aligned section on 16 bytes boundary. llvm-svn: 241674
* [LAA] Merge memchecks for accesses separated by a constant offsetSilviu Baranga2015-07-084-11/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Often filter-like loops will do memory accesses that are separated by constant offsets. In these cases it is common that we will exceed the threshold for the allowable number of checks. However, it should be possible to merge such checks, sice a check of any interval againt two other intervals separated by a constant offset (a,b), (a+c, b+c) will be equivalent with a check againt (a, b+c), as long as (a,b) and (a+c, b+c) overlap. Assuming the loop will be executed for a sufficient number of iterations, this will be true. If not true, checking against (a, b+c) is still safe (although not equivalent). As long as there are no dependencies between two accesses, we can merge their checks into a single one. We use this technique to construct groups of accesses, and then check the intervals associated with the groups instead of checking the accesses directly. Reviewers: anemet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10386 llvm-svn: 241673
* [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding supportSimon Pilgrim2015-07-082-4/+36
| | | | llvm-svn: 241671
* [yaml2obj] Use regex to match sections offsets. NFCSimon Atanasyan2015-07-082-3/+3
| | | | llvm-svn: 241669
* Allow constfolding of llvm.sin.* and llvm.cos.* intrinsicsKarthik Bhat2015-07-081-0/+22
| | | | | | | | This patch const folds llvm.sin.* and llvm.cos.* intrinsics whenever feasible. Differential Revision: http://reviews.llvm.org/D10836 llvm-svn: 241665
* llvm-objdump: Replace the -macho -raw option with a generic -raw-clang-astAdrian Prantl2015-07-081-2/+0
| | | | | | | | | | | | | | | option that works with all object container formats. Now that clang modules/PCH are object containers this option is useful to to construct pipes like llvm-objdump -raw-clang-ast foo.pcm | llvm-bcanalyzer - to inspect the AST contents in a PCH container. Will be tested via clang. Belatedly addresses review feedback for r233390. llvm-svn: 241659
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