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* [X86] Set the execution domain for vptest instruction to the integer domain.Craig Topper2017-11-111-1/+1
| | | | llvm-svn: 317973
* [globalisel][tablegen] Import signextload and zeroextload.Daniel Sanders2017-11-112-2/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
* [X86] Correct the execution domain on ROUND/VROUND instructions.Craig Topper2017-11-111-2/+2
| | | | llvm-svn: 317968
* [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter ↵Craig Topper2017-11-101-20/+8
| | | | | | | | | | | | | | handling to accept GEPs with more than 2 operands if the middle operands are all 0s Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows. This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted. We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example. Differential Revision: https://reviews.llvm.org/D39911 llvm-svn: 317947
* [asan] Use dynamic shadow on 32-bit Android.Evgeniy Stepanov2017-11-101-0/+30
| | | | | | | | | | | | | | | | | | | Summary: The following kernel change has moved ET_DYN base to 0x4000000 on arm32: https://marc.info/?l=linux-kernel&m=149825162606848&w=2 Switch to dynamic shadow base to avoid such conflicts in the future. Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation until PR35221 is fixed. This will eventually let use save one load per function. Reviewers: kcc Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D39393 llvm-svn: 317943
* [llvm-cvtres] Add support for ARM64Martin Storsjo2017-11-101-0/+15
| | | | | | | | | | | Also change some default cases into llvm_unreachable in WindowsResourceCOFFWriter, to make it easier to find if they are triggerd from within e.g. lld, which supported ARM64 earlier than llvm-cvtres did. Differential Revision: https://reviews.llvm.org/D39892 llvm-svn: 317942
* Add back target triple to test which I accidentally removed.Adrian Prantl2017-11-101-0/+1
| | | | llvm-svn: 317912
* [CVP] Remove some {s|u}add.with.overflow checks.Sanjoy Das2017-11-101-0/+369
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds logic to CVP to remove some overflow checks. It uses LVI to remove operations with at least one constant. Specifically, this can remove many overflow intrinsics immediately following an overflow check in the source code, such as: if (x < INT_MAX) ... x + 1 ... Patch by Joel Galenson! Reviewers: sanjoy, regehr Reviewed By: sanjoy Subscribers: fhahn, pirama, srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D39483 llvm-svn: 317911
* [X86] Add test case to demonstrate failure to fold the address computation ↵Craig Topper2017-11-101-2/+226
| | | | | | of a simple gather from a global array. NFC llvm-svn: 317905
* Move test into X86 subdirectory.Adrian Prantl2017-11-101-1/+0
| | | | llvm-svn: 317896
* [WebAssembly] Fix stack offsets of return values from call lowering.Jatin Bhateja2017-11-101-1/+12
| | | | | | | | | | | | | | Summary: Fixes PR35220 Reviewers: vadimcn, alexcrichton Reviewed By: alexcrichton Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin Differential Revision: https://reviews.llvm.org/D39866 llvm-svn: 317895
* [AArch64][SVE] Asm: More concise test formatFlorian Hahn2017-11-108-232/+240
| | | | | | | | | | | | | | | | | | | | | | Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file. The tests check the following: * All instructions are assembled correctly into the right encoding. * All instructions are disassembled correctly (into the preferred assembly format) * Without -mattr=+sve the instructions are not assembled. * Without -mattr=+sve the instructions are not disassembled. This patch also adds several negative tests for SVE add/sub. Patch by Sander De Smalen. Reviewed by: rengolin, fhahn Differential Revision: https://reviews.llvm.org/D39792 llvm-svn: 317894
* [X86] Add scheduling tests for DAA/DASSimon Pilgrim2017-11-101-2/+168
| | | | llvm-svn: 317892
* [X86] Test non-i64 shld/shll tests on x86_64 targets as well as i686Simon Pilgrim2017-11-101-161/+286
| | | | llvm-svn: 317888
* [X86] Add scheduling testsSimon Pilgrim2017-11-101-10/+289
| | | | | | | | - CBW etc sign extensions - CLC/CLD/CMC flag modifiers - CPUID llvm-svn: 317885
* [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the ↵Alexander Timofeev2017-11-101-0/+27
| | | | | | | | dead one Differential revision: https://reviews.llvm.org/D38754 llvm-svn: 317884
* [X86] Added TODO list for missing generic x86 instruction scheduling tests.Simon Pilgrim2017-11-102-0/+190
| | | | | | Not sure if we want to add the more exotic system instructions (IRET etc.) as well? llvm-svn: 317882
* [RegisterCoalescer] Move debug value after rematerialize trivial defKarl-Johan Karlsson2017-11-101-0/+50
| | | | | | | | | | | | | | | | | | | Summary: The associated debug value is updated when the virtual source register of a copy is completely eliminated and replaced with a rematerialize value in the defed register of the copy. As the debug value now is associated with another register it also need to be moved, otherwise the debug value isn't valid. Reviewers: aprantl Reviewed By: aprantl Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: https://reviews.llvm.org/D38024 llvm-svn: 317880
* [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.Jonas Paulsson2017-11-101-0/+75
| | | | | | | | | | | | | | | | | | | | * The method getRegAllocationHints() is now of bool type instead of void. If true is returned, regalloc (AllocationOrder) will *only* try to allocate the hints, as opposed to merely trying them before non-hinted registers. * TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with an increase in number of LOCRs. In this case, it is desired to force the hints even though there is a slight increase in spilling, because if a non-hinted register would be allocated, the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR (Load On Condition) SystemZ instruction must have both operands in either the low or high part of the 64 bit register. Reviewers: Quentin Colombet and Ulrich Weigand https://reviews.llvm.org/D36795 llvm-svn: 317879
* [X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C)Craig Topper2017-11-101-2/+37
| | | | | | Support the opposite direction as well. Also add a TODO for not being able to combine FMSUB/FNMADD/FNMSUB with FNEG. llvm-svn: 317878
* [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz ↵Yaxun Liu2017-11-1010-31/+32
| | | | | | | | | | | | | | | | environment r600 uses dummy pointer info for lowering load/store. Since dummy pointer info assumes address space 0, this causes isel failure when temporary load/store SDNodes are generated for amdgiz environment. Since the offest is not constant, FixedStack pseudo source value cannot be used to create the pointer info. This patch creates pointer info using llvm undef value. At least this provides correct address space so that isel can be done correctly. Differential Revision: https://reviews.llvm.org/D39698 llvm-svn: 317862
* [AMDGPU] Fix pointer info for pseudo source for r600Yaxun Liu2017-11-104-87/+88
| | | | | | | | | | | The pointer info for pseudo source for r600 is not correct when alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39670 llvm-svn: 317861
* [ThinLTO] Fix missing call graph edges for calls with bitcasts.Volodymyr Sapsai2017-11-101-0/+31
| | | | | | | | | | | | | | | | | | This change doesn't fix the root cause of the miscompile PR34966 as the root cause is in the linker ld64. This change makes call graph more complete allowing to have better module imports/exports. rdar://problem/35344706 Reviewers: tejohnson Reviewed By: tejohnson Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39356 llvm-svn: 317853
* [SimplifyCFG] Fix a test case.Easwaran Raman2017-11-091-1/+2
| | | | | | | This was first committed in r317845, but had the order of branch weights wrong and didn't properly check the output. llvm-svn: 317848
* Add a wrapper function to set branch weights metadata.Easwaran Raman2017-11-091-0/+39
| | | | | | | | | | | | | | Summary: This wrapper checks if there is at least one non-zero weight before setting the metadata. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39872 llvm-svn: 317845
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-092-22/+26
| | | | llvm-svn: 317841
* Fix out-of-order stepping behavior in programs with hoisted constants.Paul Robinson2017-11-092-0/+96
| | | | | | | | | | | | | | | | | | When the Constant Hoisting pass moves expensive constants into a common block, it would assign a debug location equal to the last use of that constant. While this is certainly intuitive, it places the constant in an out-of-order location, according to the debug location information. This produces out-of-order stepping when debugging programs affected by this pass. This patch creates in-order stepping behavior by merging the debug locations for hoisted constants, and the new insertion point. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D38088 llvm-svn: 317827
* Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).Adrian Prantl2017-11-091-0/+64
| | | | | | rdar://problem/27139077 llvm-svn: 317825
* [SLP] Fix PR23510: Try to find best possible vectorizable stores.Alexey Bataev2017-11-091-15/+10
| | | | | | | | | | | | | | | | | | Summary: The analysis of the store sequence goes in straight order - from the first store to the last. Bu the best opportunity for vectorization will happen if we're going to use reverse order - from last store to the first. It may be best because usually users have some initialization part + further processing and this first initialization may confuse SLP vectorizer. Reviewers: RKSimon, hfinkel, mkuper, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39606 llvm-svn: 317821
* [Reassociate] auto-generate test checks; NFCSanjay Patel2017-11-094-47/+60
| | | | llvm-svn: 317819
* [Reassociate] don't name values "tmp"; NFCISanjay Patel2017-11-098-253/+279
| | | | | | | | | | The toxic stew of created values named 'tmp' and tests that already have values named 'tmp' and CHECK lines looking for values named 'tmp' causes bad things to happen in our test line auto-generation scripts because it wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to avoid that. llvm-svn: 317818
* revert r317809 - [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-14/+4
| | | | | | | The reassociate pass generates named values such as "%tmp2" which trips up the script's regex's because the script uses a 'TMP' prefix for unnamed values (%2). llvm-svn: 317810
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-4/+14
| | | | llvm-svn: 317809
* [SystemZ] Add support for the "o" inline asm constraintUlrich Weigand2017-11-091-0/+10
| | | | | | | | | We don't really need any special handling of "offsettable" memory addresses, but since some existing code uses inline asm statements with the "o" constraint, add support for this constraint for compatibility purposes. llvm-svn: 317807
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-66/+73
| | | | llvm-svn: 317806
* [Reassociate] add check lines; NFCSanjay Patel2017-11-091-1/+11
| | | | llvm-svn: 317805
* [Reassociate] add tests with 'reassoc' FMF and regenerate checks; NFCSanjay Patel2017-11-091-84/+254
| | | | llvm-svn: 317804
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-092-9/+34
| | | | | | | | | | | | | | Correct the definition of 'j' as being unavailable for microMIPS32R6 and provide the 'b' assembly idiom for codegen purposes for microMIPS32r3. Provide the necessary 'br' pattern for microMIPS32R6 as it now longer incorrectly uses the 'j' instruction. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39741 llvm-svn: 317801
* [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.pyAlex Bradbury2017-11-091-38/+58
| | | | | | | No real change, but makes it marginally easier to merge the remainder of the out-of-tree patches. llvm-svn: 317796
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-093-0/+162
| | | | llvm-svn: 317791
* Reapply: Allow yaml2obj to order implicit sections for ELFDave Lee2017-11-092-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change allows yaml input to control the order of implicitly added sections (`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a placeholder section of the given name to the Sections field. This change is to support changes in D39582, where it is desirable to control the location of the `.dynsym` section. This reapplied version fixes: 1. use of a function call within an assert 2. failing lld test which has an unnamed section 3. incorrect section count when given an unnamed section Additionally, one more test to cover the unnamed section failure. Reviewers: compnerd, jakehehrlich Reviewed By: jakehehrlich Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39749 llvm-svn: 317789
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-092-0/+36
| | | | llvm-svn: 317788
* Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.Andrew V. Tischenko2017-11-092-16/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D39802 llvm-svn: 317785
* Add -print-schedule scheduling comments to inline asm.Andrew V. Tischenko2017-11-092-156/+156
| | | | | | Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
* [X86] Make X86ISD::FMADDS3 isel patterns commutable.Craig Topper2017-11-091-0/+95
| | | | | | This was missed when FMADDS3 was split from X86ISD::FMADDS3_RND. llvm-svn: 317769
* [GVN PRE] Patch the source for Phi node in PRESerguei Katkov2017-11-092-0/+88
| | | | | | | | | | | | | | | | | | | We must patch all existing incoming values of Phi node, otherwise it is possible that we can see poison where program does not expect to see it. This is the similar what GVN does. The added test test/Transforms/GVN/PRE/pre-jt-add.ll shows an example of wrong optimization done by jump threading due to GVN PRE did not patch existing incoming value. Reviewers: mkazantsev, wmi, dberlin, davide Reviewed By: dberlin Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D39637 llvm-svn: 317768
* [llvm-cov] Fix more -path-equivalence test bugsVedant Kumar2017-11-093-1/+1
| | | | llvm-svn: 317764
* [llvm-cov] Fix a -path-equivalence bug in a testVedant Kumar2017-11-091-2/+2
| | | | llvm-svn: 317763
* [llvm-cov] Don't render empty region marker linesVedant Kumar2017-11-091-1/+1
| | | | | | | This fixes an issue where llvm-cov prints an empty line, thinking it needs to display region markers, when it actually doesn't. llvm-svn: 317762
* [Coverage] Use the wrapped segment when a line has entry segmentsVedant Kumar2017-11-0917-92/+57
| | | | | | | | | We've worked around bugs in the frontend by ignoring the count from wrapped segments when a line has at least one region entry segment. Those frontend bugs are now fixed, so it's time to regenerate the checked-in covmapping files and remove the workaround. llvm-svn: 317761
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