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* [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-0/+31
| | | | | | | | | | | | Summary: Depends on D3957 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3958 llvm-svn: 210775
* [mips][mips64r6] Add R_MIPS_PC19_S2Zoran Jovanovic2014-06-122-11/+41
| | | | | | Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-126-17/+17
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-124-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders2014-06-122-32/+307
| | | | | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 llvm-svn: 210763
* [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-123-15/+241
| | | | | | | | | | | | | | | | Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
* [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit ↵Andrea Di Biagio2014-06-121-0/+277
| | | | | | | | | | | vectors. This patch adds target combine rules to match: - [AVX] Horizontal add/sub of packed single/double precision floating point values from 256-bit vectors; - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors. llvm-svn: 210761
* [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ↵Daniel Sanders2014-06-129-42/+384
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
* [mips] Move CHECK lines to the same line as the instruction it's testingMatheus Almeida2014-06-122-8/+4
| | | | | | | | for consistency with the other tests. No functional changes. llvm-svn: 210757
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-122-6/+22
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* [FastISel][x86] Add testcase for r210719.Juergen Ributzka2014-06-121-0/+24
| | | | llvm-svn: 210746
* [x86] Improve frameaddress test from r210709.Juergen Ributzka2014-06-121-10/+27
| | | | llvm-svn: 210743
* [FastISel] Add support for the stackmap intrinsic.Juergen Ributzka2014-06-121-0/+165
| | | | | | This implements target-independent FastISel lowering for the stackmap intrinsic. llvm-svn: 210742
* Fix verifier for GlobalAliases to avoid recursing into global initializers.Bob Wilson2014-06-121-0/+4
| | | | | | | | | | | The verifier follows GlobalAlias operands so that it can detect cycles of alias definitions. It was doing this in a way that caused it to also recurse through initializers for the GlobalValue aliasees, and it would fail when an initializer refers to a global that is a declaration and not a definition. This patch causes it to stop recursing when it hits a global definition. <rdar://problem/17277451> llvm-svn: 210734
* Teach LoopUnrollPass to respect loop unrolling hints in metadata.Eli Bendersky2014-06-111-0/+285
| | | | | | | | | | See http://reviews.llvm.org/D4090 for more details. The Clang change that produces this metadata was committed in r210667 Patch by Mark Heffernan. llvm-svn: 210721
* [FastISel][X86] Add support for the sqrt intrinsic.Juergen Ributzka2014-06-111-0/+26
| | | | llvm-svn: 210720
* [FastISel][X86] Add support for the frameaddress intrinsic.Juergen Ributzka2014-06-114-33/+27
| | | | llvm-svn: 210709
* [AArch64] Basic Sched Model for Cortex-A57.Chad Rosier2014-06-111-0/+112
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org> Differential Revision: http://reviews.llvm.org/D4008 llvm-svn: 210705
* ARM: honor hex immediate formatting for ldr/str i12 offsets.Jim Grosbach2014-06-111-0/+6
| | | | | | | | | | | | | | | | | Previously we would always print the offset as decimal, regardless of the formatting requested. Now we use the formatImm() helper so the value is printed as the client (LLDB in the motivating example) requested. Before: ldr.w r8, [sp, #180] @ always After: ldr.w r8, [sp, #0xb4] @ when printing hex immediates ldr.w r8, [sp, #0180] @ when printing decimal immediates rdar://17237103 llvm-svn: 210701
* llvm-mc: Add option for prefering hex format disassembly.Jim Grosbach2014-06-113-5/+5
| | | | | | | | | Previously there was a separate mode entirely (--hdis vs. --disassemble). It makes a bit more sense for the immediate printing style to be a flag for --disassmeble rather than an entirely different thing. llvm-svn: 210700
* R600/SI: Fix bitcast between v2i32 and f64Matt Arsenault2014-06-111-5/+25
| | | | | | | | | | This is the same problem fixed in r210664 for more types. The test passes without this fix. For some reason I'm only hitting this when creating selects lowered to v2i32 selects. llvm-svn: 210692
* Use std::error_code instead of llvm::error_code.Rafael Espindola2014-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea of this patch is to turn llvm/Support/system_error.h into a transitional header that just brings in the erorr_code api to the llvm namespace. I will remove it shortly afterwards. The cases where the general idea needed some tweaking: * std::errc is a namespace in msvc, so we cannot use "using std::errc". I could add an #ifdef, but there were not that many uses, so I just added std:: to them in this patch. * Template specialization had to be moved to the std namespace in this patch set already. * The msvc implementation of default_error_condition doesn't seem to provide the same transformations as we need. Not too surprising since the standard doesn't actually say what "equivalent" means. I fixed the problem by keeping our old mapping and using it at error_code construction time. Despite these shortcomings I think this is still a good thing. Some reasons: * The different implementations of system_error might improve over time. * It removes 925 lines of code from llvm already. * It removes 6313 bytes from the text segment of the clang binary when it is built with gcc and 2816 bytes when building with clang and libstdc++. llvm-svn: 210687
* [Reassociate] FileCheckize and cleanup a few testcases. No functional changeChad Rosier2014-06-1116-230/+275
| | | | | | intended. llvm-svn: 210685
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-112-0/+262
| | | | llvm-svn: 210680
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-111-0/+16
| | | | llvm-svn: 210678
* R600/SI: Use LDS atomic inc / decMatt Arsenault2014-06-111-0/+38
| | | | llvm-svn: 210677
* R600/SI: Add other LDS atomic operationsMatt Arsenault2014-06-111-0/+208
| | | | llvm-svn: 210676
* R600/SI: Fix backwards names for local atomic instructions.Matt Arsenault2014-06-112-8/+8
| | | | | | | The manual lists them as *_RTN_U32, not *_U32_RTN, which is more consistent with how every other sized instruction is named. llvm-svn: 210674
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-112-30/+60
| | | | | | | Use patterns that will also match the immediate offset to match the normal read / writes. llvm-svn: 210673
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-113-0/+227
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-112-5/+99
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
* [mips][mips64r6] Improve tests affected by the changes to multiplies and dividesDaniel Sanders2014-06-115-83/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MIPS32r6/MIPS64r6 support has not been added yet. inlineasm-cnstrnt-reg.ll: Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6 when -integrated-as is the default. We can't change the mnemonic since the LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no instructions that use LO. 2008-08-01-AsmInline.ll: Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit different code and this is a regression test. mips64instrs.ll and mips64muldiv.ll Check registers and the way the multiply is used in m1 divrem.ll Check registers and use multiple filecheck prefixes to limit redundancy Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida Reviewed By: matheusalmeida Subscribers: matheusalmeida Differential Revision: http://reviews.llvm.org/D3894 llvm-svn: 210656
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-1112-0/+68
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* Add AVX512 masked leadz instrinsic support.Cameron McInally2014-06-111-1/+33
| | | | llvm-svn: 210652
* Improve the test for inlining of __no_debug__ functions.Evgeniy Stepanov2014-06-111-1/+1
| | | | llvm-svn: 210645
* [X86] Refactor the logic to select horizontal adds/subs to a helper function.Andrea Di Biagio2014-06-111-18/+83
| | | | | | | | | | | | | | | This patch moves part of the logic implemented by the target specific combine rules added at r210477 to a separate helper function. This should make easier to add more rules for matching AVX/AVX2 horizontal adds/subs. This patch also fixes a problem caused by a wrong check performed on indices of extract_vector_elt dag nodes in input to the scalar adds/subs. New tests have been added to verify that we correctly check indices of extract_vector_elt dag nodes when selecting a horizontal operation. llvm-svn: 210644
* Global merge for global symbols.Jiangning Liu2014-06-117-65/+212
| | | | | | | | This commit is to improve global merge pass and support global symbol merge. The global symbol merge is not enabled by default. For aarch64, we need some more back-end fix to make it really benifit ADRP CSE. llvm-svn: 210640
* Rename global-merge to enable-global-merge.Jiangning Liu2014-06-112-8/+8
| | | | llvm-svn: 210639
* [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.Juergen Ributzka2014-06-101-0/+337
| | | | llvm-svn: 210610
* Rearrange the CHECK lines in this test to make failure more obvious.Reid Kleckner2014-06-101-17/+16
| | | | llvm-svn: 210575
* Revert "Patch by Ray Donnelly to print register names instead of numbers."Reid Kleckner2014-06-101-4/+4
| | | | | | | | | | | | | This reverts commit r206683. The code was confusing SEH register numbers with DWARF register numbers. The test case it was committed with was obviously incorrect. The disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg %rbp', and other exciting things. Noticed by Vadim Chugunov. llvm-svn: 210574
* Fix error in tablegen when either operand of !if is an empty list.Matt Arsenault2014-06-101-0/+7
| | | | | | !if([Something], []) would error with "No type for list". llvm-svn: 210572
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-101-0/+51
| | | | llvm-svn: 210569
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+91
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-0/+203
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-102-0/+87
| | | | llvm-svn: 210564
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-101-7/+56
| | | | llvm-svn: 210563
* Do Materialize Floating Point in Mips Fast-IselReed Kotler2014-06-101-0/+38
| | | | | | | | | | | | | | | | | Summary: Implement materialize of floating point literals in Mips Fast-Isel Reopened version of D3659 Test Plan: simplestorefp1.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4071 llvm-svn: 210546
* [X86] Improved target combine rules for selecting horizontal add/sub.Andrea Di Biagio2014-06-101-1/+85
| | | | | | | | | | | | | This patch slightly changes the algorithm introduced at revision 210477 to fix a problem where the algorithm was producing incorrect code for the VEX.256 encoded versions of horizontal add/sub. For these cases, we now try to split the two 256-bit vectors into 128-bit chunks before emitting horizontal add/sub dag nodes. Added a new test case into haddsub-2.ll. llvm-svn: 210545
* [X86] AVX512: Add vmovntdqaAdam Nemet2014-06-102-0/+17
| | | | | | Along with the corresponding intrinsic and tests. llvm-svn: 210543
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