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* Debugging infomration is encoded in llvm IR using metadata. This is designedDevang Patel2010-07-011-0/+47
| | | | | | | | | such a way that debug info for symbols preserved even if symbols are optimized away by the optimizer. Add new special pass to remove debug info for such symbols. llvm-svn: 107416
* Move SSE3 Move patterns to a more appropriate sectionBruno Cardoso Lopes2010-07-012-0/+64
| | | | | | Add AVX SSE3 packed horizontal and & sub instructions llvm-svn: 107405
* Add AVX SSE3 packed addsub instructionsBruno Cardoso Lopes2010-07-012-0/+32
| | | | llvm-svn: 107404
* Temporarily disable on-demand fast-isel.Dan Gohman2010-07-011-1/+1
| | | | llvm-svn: 107393
* Teach fast-isel to avoid loading a value from memory when it's alreadyDan Gohman2010-07-011-0/+23
| | | | | | | available in a register. This is pretty primitive, but it reduces the number of instructions in common testcases by 4%. llvm-svn: 107380
* Enable on-demand fast-isel.Dan Gohman2010-07-011-2/+3
| | | | llvm-svn: 107377
* Add AVX SSE3 replicate and convert instructionsBruno Cardoso Lopes2010-07-012-0/+72
| | | | llvm-svn: 107375
* Teach X86FastISel to fold constant offsets and scaled indices inDan Gohman2010-07-011-0/+19
| | | | | | the same address. llvm-svn: 107373
* - Add AVX SSE2 Move doubleword and quadword instructions.Bruno Cardoso Lopes2010-07-012-0/+64
| | | | | | | | - Add encode bits for VEX_W - All 128-bit SSE 1 & SSE2 instructions that are described in the .td file now have a AVX encoded form already working. llvm-svn: 107365
* Test for the -filelist fix.Mikhail Glushenkov2010-07-011-0/+3
| | | | llvm-svn: 107363
* Remove all debug info related named mdnodes.Devang Patel2010-06-301-0/+28
| | | | llvm-svn: 107323
* Add AVX SSE2 mask creation and conditional store instructionsBruno Cardoso Lopes2010-06-302-0/+16
| | | | llvm-svn: 107306
* Revert the part of r107257 which introduced new logic for usingDan Gohman2010-06-301-3/+4
| | | | | | | nsw and nuw flags from IR Instructions. On further consideration, this isn't valid. llvm-svn: 107298
* Add AVX SSE2 packed integer extract/insert instructionsBruno Cardoso Lopes2010-06-302-0/+24
| | | | llvm-svn: 107293
* Add a testcase for scev-aa's new capability.Dan Gohman2010-06-301-3/+24
| | | | llvm-svn: 107258
* Add AVX SSE2 integer unpack instructionsBruno Cardoso Lopes2010-06-302-0/+128
| | | | llvm-svn: 107246
* Add AVX SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-302-0/+48
| | | | llvm-svn: 107245
* Add AVX SSE2 pack with saturation integer instructionsBruno Cardoso Lopes2010-06-302-0/+48
| | | | llvm-svn: 107241
* Add AVX SSE2 integer packed compare instructionsBruno Cardoso Lopes2010-06-302-0/+96
| | | | llvm-svn: 107240
* - Add AVX form of all SSE2 logical instructionsBruno Cardoso Lopes2010-06-302-0/+280
| | | | | | - Add VEX encoding bits to x86 MRM0r-MRM7r llvm-svn: 107238
* Add variables into a scope before constructing scope DIE otherwise variables ↵Devang Patel2010-06-301-0/+52
| | | | | | won't be included DIE tree. llvm-svn: 107228
* Add *several* AVX integer packed binop instructionsBruno Cardoso Lopes2010-06-292-0/+432
| | | | llvm-svn: 107225
* Fix ScalarEvolution's tripcount computation for chains of loopsDan Gohman2010-06-291-2/+64
| | | | | | | where each loop's induction variable's start value is the exit value of a preceding loop. llvm-svn: 107224
* Add AVX ld/st XCSR register.Bruno Cardoso Lopes2010-06-292-0/+24
| | | | | | Add VEX encoding bits for MRMXm x86 form llvm-svn: 107204
* Fix the handling of partial redefines in the fast register allocator.Jakob Stoklund Olesen2010-06-291-0/+22
| | | | | | | | | | | A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. llvm-svn: 107193
* Fix a register scavenger crash when dealing with undefined subregs.Bob Wilson2010-06-291-0/+15
| | | | | | | The LowerSubregs pass needs to preserve implicit def operands attached to EXTRACT_SUBREG instructions when it replaces those instructions with copies. llvm-svn: 107189
* Add AVX non-temporal storesBruno Cardoso Lopes2010-06-292-0/+24
| | | | llvm-svn: 107178
* Add a few more interesting testcases.Dan Gohman2010-06-291-0/+21
| | | | llvm-svn: 107177
* Add sqrt, rsqrt and rcp AVX instructionsBruno Cardoso Lopes2010-06-292-0/+129
| | | | llvm-svn: 107166
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-1/+1
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* Looks like this test is missing an XFAIL line.Duncan Sands2010-06-291-0/+1
| | | | llvm-svn: 107134
* PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.Evan Cheng2010-06-291-25/+68
| | | | llvm-svn: 107122
* Reapply my if-conversion cleanup from svn r106939 with fixes.Bob Wilson2010-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 changes relative to the previous version of the patch: 1) For the "simple" if-conversion case, there's no need to worry about RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators are ignored in this context, so RemoveExtraEdges does the right thing. This might break someday if we ever treat indirect branches (BRIND) as predicable, but for now, I just removed this part of the patch, because in the case where we do not add an unconditional branch, we rely on keeping the fall-through edge to CvtBBI (which is empty after this transformation). The change relative to the previous patch is: @@ -1036,10 +1036,6 @@ IterIfcvt = false; } - // RemoveExtraEdges won't work if the block has an unanalyzable branch, - // which is typically the case for IfConvertSimple, so explicitly remove - // CvtBBI as a successor. - BBI.BB->removeSuccessor(CvtBBI->BB); RemoveExtraEdges(BBI); // Update block info. BB can be iteratively if-converted. 2) My patch exposed a bug in the code for merging the tail of a "diamond", which had previously never been exercised. The code was simply checking that the tail had a single predecessor, but there was a case in MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was neither edge of the diamond. I added the following change to check for that: @@ -1276,7 +1276,18 @@ // tail, add a unconditional branch to it. if (TailBB) { BBInfo TailBBI = BBAnalysis[TailBB->getNumber()]; - if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) { + bool CanMergeTail = !TailBBI.HasFallThrough; + // There may still be a fall-through edge from BBI1 or BBI2 to TailBB; + // check if there are any other predecessors besides those. + unsigned NumPreds = TailBB->pred_size(); + if (NumPreds > 1) + CanMergeTail = false; + else if (NumPreds == 1 && CanMergeTail) { + MachineBasicBlock::pred_iterator PI = TailBB->pred_begin(); + if (*PI != BBI1->BB && *PI != BBI2->BB) + CanMergeTail = false; + } + if (CanMergeTail) { MergeBlocks(BBI, TailBBI); TailBBI.IsDone = true; } else { With these fixes, I was able to run all the SingleSource and MultiSource tests successfully. llvm-svn: 107110
* Add an Intraprocedural form of BasicAliasAnalysis, which aims toDan Gohman2010-06-291-0/+42
| | | | | | | properly handles instructions and arguments defined in different functions, or across recursive function iterations. llvm-svn: 107109
* Described the missing AVX forms of SSE2 convert instructionsBruno Cardoso Lopes2010-06-292-0/+103
| | | | llvm-svn: 107108
* The comment string does not match for all targets. PowerPC uses ;.Devang Patel2010-06-291-0/+1
| | | | llvm-svn: 107103
* Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson2010-06-281-0/+10
| | | | | | | can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. llvm-svn: 107097
* Refix XTARGET. Previous attempt matches on powerpc-apple-darwin,Dale Johannesen2010-06-281-1/+1
| | | | | | although I don't see why. llvm-svn: 107090
* Attempt to fix XTARGET.Dale Johannesen2010-06-281-1/+1
| | | | llvm-svn: 107088
* Use DW_FORM_addr for DW_AT_entry_pc.Devang Patel2010-06-281-0/+48
| | | | llvm-svn: 107085
* In asm's, output operands with matching input constraintsDale Johannesen2010-06-283-3/+14
| | | | | | | | have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
* Constant fold x == undef to undef.Dan Gohman2010-06-281-0/+23
| | | | llvm-svn: 107074
* Fix Value::stripPointerCasts and BasicAA to avoid trouble onDan Gohman2010-06-281-0/+16
| | | | | | | code in unreachable blocks, which have have use-def cycles. This fixes PR7514. llvm-svn: 107071
* Remove this weak test.Devang Patel2010-06-281-16/+0
| | | | llvm-svn: 107059
* Testcase for llvm-gcc fix 107051.Dale Johannesen2010-06-281-0/+21
| | | | llvm-svn: 107052
* Don't write temporary files in test directoryJakob Stoklund Olesen2010-06-281-1/+1
| | | | llvm-svn: 107049
* Add a triple so test runs on Linux as well.Jakob Stoklund Olesen2010-06-281-0/+1
| | | | llvm-svn: 107045
* Add more special treatment for inline asm in RegAllocFast.Jakob Stoklund Olesen2010-06-282-1/+22
| | | | | | | | | | | | When an instruction has tied operands and physreg defines, we must take extra care that the tied operands conflict with neither physreg defs nor uses. The special treatment is given to inline asm and instructions with tied operands / early clobbers and physreg defines. This fixes PR7509. llvm-svn: 107043
* Preserve deleted function's local variables' debug info.Devang Patel2010-06-281-0/+14
| | | | | | Radar 8122864. llvm-svn: 107027
* Make this test darwin specific.Devang Patel2010-06-281-1/+1
| | | | llvm-svn: 107025
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