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* [WebAssembly] MC: Support for init_array and fini_arraySam Clegg2017-10-031-0/+96
| | | | | | Differential Revision: https://reviews.llvm.org/D37757 llvm-svn: 314783
* [llvm-cov] Hide files with no coverage from the index when filtering by nameSean Eveson2017-10-031-0/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D38457 llvm-svn: 314782
* [DebugInfo] Handle endianness when moving debug info for split integer ↵Bjorn Pettersson2017-10-031-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values (reapplied) Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Original patch was reverted due to using -stop-after=isel in the test case (but that is only working when AMDGPU target is included in the llc build). The test case has now been updated to use -stop-before=expand-isel-pseudos instead. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314781
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-0341-2001/+2176
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* [X86][SSE] Add support for shuffle combining from PACKSS/PACKUSSimon Pilgrim2017-10-031-16/+4
| | | | | | Mentioned in D38472 llvm-svn: 314777
* [X86][SSE] Add support for PACKSS/PACKUS constant foldingSimon Pilgrim2017-10-033-68/+48
| | | | | | Pulled out of D38472 llvm-svn: 314776
* [llvm-readobj][RISCV] Pretty-print RISCV e_flagsAlex Bradbury2017-10-031-0/+7
| | | | llvm-svn: 314772
* [RISCV] Add missed test case for r314770Alex Bradbury2017-10-032-0/+19
| | | | | | | Differential Revision: https://reviews.llvm.org/D38311 Patch by https://reviews.llvm.org/D38311 llvm-svn: 314771
* [ObjectYAML] Handle SHF_COMPRESSEDShoaib Meenai2017-10-031-0/+28
| | | | | | | | | This was previously being silently dropped by obj2yaml and caused parsing errors with yaml2obj. Differential Revision: https://reviews.llvm.org/D38490 llvm-svn: 314768
* [X86] Provide the LSDA pointer with RIP relative addressing if necessaryMartin Storsjo2017-10-031-1/+1
| | | | | | | | | | | | | This makes sure the LSDA pointer isn't truncated to 32 bit. Make LowerINTRINSIC_WO_CHAIN a member function instead of a static function, so that it can use the getGlobalWrapperKind method. This solves the second half of the issues mentioned in PR34720. Differential Revision: https://reviews.llvm.org/D38343 llvm-svn: 314767
* [Lint] Avoid failed assertion by fetching the proper pointer typeMikael Holmen2017-10-031-0/+23
| | | | | | | | | | | | | | | | | | | | | Summary: When checking if a constant expression is a noop cast we fetched the IntPtrType by doing DL->getIntPtrType(V->getType())). However, there can be cases where V doesn't return a pointer, and then getIntPtrType() triggers an assertion. Now we pass DataLayout to isNoopCast so the method itself can determine what the IntPtrType is. Reviewers: arsenm Reviewed By: arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D37894 llvm-svn: 314763
* [Legalizer] Add support for G_OR NarrowScalar.Quentin Colombet2017-10-031-11/+48
| | | | | | | | | | | | | | Legalize bitwise OR: A = BinOp<Ty> B, C into: B1, ..., BN = G_UNMERGE_VALUES B C1, ..., CN = G_UNMERGE_VALUES C A1 = BinOp<Ty/N> B1, C2 ... AN = BinOp<Ty/N> BN, CN A = G_MERGE_VALUES A1, ..., AN llvm-svn: 314760
* [X86] Add AVX512 check lines to the cost model truncate test.Craig Topper2017-10-031-0/+13
| | | | llvm-svn: 314758
* [InstSimplify] teach SimplifySelectInst() to fold more vector selectsHaicheng Wu2017-10-021-0/+8
| | | | | | | | | | | | Call ConstantFoldSelectInstruction() to fold cases like below select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3> All operands are constants and the condition has mixed true and false conditions. Differential Revision: https://reviews.llvm.org/D38369 llvm-svn: 314741
* [PassManager] Retire cl::opt that have been set for a while. NFCI.Davide Italiano2017-10-023-3/+3
| | | | llvm-svn: 314740
* [PowerPC] Revert r314666.Tim Shen2017-10-021-68/+0
| | | | | | | | | See https://reviews.llvm.org/D38172. I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply revert it. llvm-svn: 314739
* [PowerPC] Temporarily disable the test introduced by r314666Tim Shen2017-10-021-0/+2
| | | | | | See https://reviews.llvm.org/D38172 for details. llvm-svn: 314732
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-10-0285-349/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues addressed since original review: - Avoid bug in regalloc greedy/machine verifier when forwarding to use in an instruction that re-defines the same virtual register. - Fixed bug when forwarding to use in EarlyClobber instruction slot. - Fixed incorrect forwarding to register definitions that showed up in explicit_uses() iterator (e.g. in INLINEASM). - Moved removal of dead instructions found by LiveIntervals::shrinkToUses() outside of loop iterating over instructions to avoid instructions being deleted while pointed to by iterator. - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 314729
* [X86] Run dos2unix on two disassembler tests.Craig Topper2017-10-022-1854/+1854
| | | | llvm-svn: 314727
* llvm-dwarfdump: support the --ignore-case option.Adrian Prantl2017-10-022-0/+8
| | | | llvm-svn: 314723
* AMDGPU: Fix potentially incorrectly matching check linesMatt Arsenault2017-10-021-8/+8
| | | | | | | | These check lines are supposed to make sure the new d16 load instructions aren't used, but the expected instruction name is a prefix of the incorrect instruction name. llvm-svn: 314714
* [InstCombine] auto-generate complete checks; NFCSanjay Patel2017-10-021-39/+54
| | | | llvm-svn: 314712
* [InstCombine] add icmp (shr X, Y), 0 test; NFCSanjay Patel2017-10-021-0/+14
| | | | llvm-svn: 314710
* Add support for Myriad ma2x8x series of CPUsWalter Lee2017-10-021-0/+14
| | | | | | | | | | | | Summary: Also add support for some older Myriad CPUs that were missing. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37552 llvm-svn: 314705
* Move the stripping of invalid debug info from the Verifier to AutoUpgrade.Adrian Prantl2017-10-0231-62/+65
| | | | | | | | | | | | | | | | | | | | | | | | This came out of a recent discussion on llvm-dev (https://reviews.llvm.org/D38042). Currently the Verifier will strip the debug info metadata from a module if it finds the dbeug info to be malformed. This feature is very valuable since it allows us to improve the Verifier by making it stricter without breaking bcompatibility, but arguable the Verifier pass should not be modifying the IR. This patch moves the stripping of broken debug info into AutoUpgrade (UpgradeDebugInfo to be precise), which is a much better location for this since the stripping of malformed (i.e., produced by older, buggy versions of Clang) is a (harsh) form of AutoUpgrade. This change is mostly NFC in nature, the one big difference is the behavior when LLVM module passes are introducing malformed debug info. Prior to this patch, a NoAsserts build would have printed a warning and stripped the debug info, after this patch the Verifier will report a fatal error. I believe this behavior is actually more desirable anyway. Differential Revision: https://reviews.llvm.org/D38184 llvm-svn: 314699
* [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> ↵Sanjay Patel2017-10-021-1/+1
| | | | | | icmp X, (C2<<C1) llvm-svn: 314698
* [InstCombine] add icmp (lshr X, C1), C2 test; NFCSanjay Patel2017-10-021-0/+15
| | | | llvm-svn: 314696
* Update getMergedLocation to check the instruction type and merge properly.Dehao Chen2017-10-021-9/+13
| | | | | | | | | | | | | | Summary: If the merged instruction is call instruction, we need to set the scope to the closes common scope between 2 locations, otherwise it will cause trouble when the call is getting inlined. Reviewers: dblaikie, aprantl Reviewed By: dblaikie, aprantl Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D37877 llvm-svn: 314694
* CodeView symbol dumper: use symbolic names for registersHans Wennborg2017-10-028-29/+29
| | | | | | https://reviews.llvm.org/D38469 llvm-svn: 314690
* Eliminate ftrunc if source is know to be roundedStanislav Mekhanoshin2017-10-021-0/+92
| | | | | | Differential Revision: https://reviews.llvm.org/D38421 llvm-svn: 314688
* [dwarfdump] Add -show-formJonas Devlieghere2017-10-022-1/+42
| | | | | | | | | This enables printing of DWARF form types after the DWARF attribute types. Differential revision: https://reviews.llvm.org/D38459 llvm-svn: 314685
* [X86][SSE] Add PACKSS/PACKUS constant folding tests Simon Pilgrim2017-10-023-16/+214
| | | | llvm-svn: 314682
* Regenerate test (missing broadcast constant comments). NFCI.Simon Pilgrim2017-10-021-8/+8
| | | | | | Still avoiding the floating point comments to prevent linux/windows discrepancies. llvm-svn: 314681
* Regenerate test (missing broadcast constant comments). NFCI.Simon Pilgrim2017-10-021-3/+3
| | | | llvm-svn: 314680
* Regenerate test. NFCI.Simon Pilgrim2017-10-021-2/+0
| | | | llvm-svn: 314679
* [AsmParser] Support GAS's .print directiveCoby Tayree2017-10-021-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D38448 llvm-svn: 314674
* [Debug info] Handle endianness when moving debug info for split integer valuesBjorn Pettersson2017-10-021-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314666
* [PowerPC] support ZERO_EXTEND in tryBitPermutationHiroshi Inoue2017-10-021-0/+23
| | | | | | | | | | | | | | | | | | | This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI. Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction. For example, we allow these nodes t9: i32 = add t7, Constant:i32<1> t11: i32 = and t9, Constant:i32<255> t12: i64 = zero_extend t11 t14: i64 = shl t12, Constant:i64<2> to be folded into a rotate-and-mask instruction. Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF]; Differential Revision: https://reviews.llvm.org/D37514 llvm-svn: 314655
* [X86][LLVM]Expanding Supports lowerInterleaved{store|load}() in ↵Michael Zuckerman2017-10-023-865/+507
| | | | | | | | | | | | | | | | | | | X86InterleavedAccess (VF64 stride 3-4) I continue to support different VF interleaved and in this pass for this patch, I added the vf64 stride3 support for both load and store. I also added support fot the stride4 store. Reviewers: 1. zvi 2. dorit 3. igorb 4. guyblank Differential Revision: https://reviews.llvm.org/D37687 Change-Id: I3d238efedf217d1768b348d710de1efa2f19d27b llvm-svn: 314651
* [Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman2017-10-021-0/+86
| | | | | | | | | | | | | HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 314642
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-0/+9
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-017-19/+19
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* [X86][SSE] Add faux shuffle combining support for PACKUSSimon Pilgrim2017-10-012-22/+6
| | | | llvm-svn: 314631
* [X86][AVX2] Simplify PACKUS combine testSimon Pilgrim2017-10-011-3/+3
| | | | | | Trying to use a AND mask is tricky as after legalization its nigh impossible for computeKnownBits to do anything with it llvm-svn: 314630
* [X86][SSE] Improve shuffle combining of PACKSS instructions.Simon Pilgrim2017-10-012-14/+6
| | | | | | Support unary packing and fix the faux shuffle mask for vectors larger than 128 bits. llvm-svn: 314629
* [X86][SSE] Add shuffle combining tests with PACKSS/PACKUSSimon Pilgrim2017-10-012-0/+156
| | | | llvm-svn: 314628
* pre-commit adding test for broadcastm patternJina Nahias2017-10-011-0/+263
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: Ifbc4189549f2f59995019a86f85f989c04e4d37d llvm-svn: 314626
* Revert r314579: "Recommi r314561 after fixing over-debug assertion".Daniel Jasper2017-10-014-302/+0
| | | | | | | | | | | | And follow-up r314585. Leads to segfaults. I'll forward reproduction instructions to the patch author. Also, for a recommit, still add the original patch description. Otherwise, it becomes really tedious to find out what a patch actually does. The fact that it is a recommit with a fix is somewhat secondary. llvm-svn: 314622
* Adding test for interleved, case stride 4 vf64 store<NFC>.Michael Zuckerman2017-10-012-0/+324
| | | | | Change-Id: I9ea62aac81b763c83d26613dca6fcd846997a017 llvm-svn: 314621
* Separate the logic when handling indirect calls in SamplePGO ThinLTO compile ↵Dehao Chen2017-10-012-5/+5
| | | | | | | | | | | | | | | | phase and other phases. Summary: In SamplePGO ThinLTO compile phase, we will not invoke ICP as it may introduce confusion to the 2nd annotation. This patch extracted that logic and makes it clearer before profile annotation. In the mean time, we need to make function importing process both inlined callsites as well as not promoted indirect callsites. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D38094 llvm-svn: 314619
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