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* [ARM] GlobalISel: Support G_BRDiana Picus2017-07-133-0/+52
| | | | | | | | This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904
* [DAGCombiner] Fix issue with rotate combines asserting if the constant value ↵Simon Pilgrim2017-07-131-0/+27
| | | | | | types differ from the result type. llvm-svn: 307900
* [ARM] Fix typo in test added in r307889Florian Hahn2017-07-131-1/+1
| | | | | | | | | This fixes the following test failure: LLVM :: Transforms/Inline/ARM/inline-target-attr.ll Sorry for any inconenience. llvm-svn: 307892
* [ARM] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-07-132-0/+62
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. As some subtarget features provide different instructions depending on whether they are set or unset (e.g. ThumbMode and ModeSoftFloat), we use a whitelist of target-features describing hardware capabilities only. Reviewers: kristof.beyls, rengolin, t.p.northover, SjoerdMeijer, peter.smith, silviu.baranga, efriedma Reviewed By: SjoerdMeijer, efriedma Subscribers: dschuff, efriedma, aemerson, sdardis, javed.absar, arichardson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34697 llvm-svn: 307889
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-0/+15
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* Add original reproducer for r307754 / PR33689Mikael Holmen2017-07-131-0/+53
| | | | | | | Apparently I managed to drop the test case between two revisions in Phabricator: https://reviews.llvm.org/D35003 llvm-svn: 307887
* [llvm-objdump] Correctly distinguish between the MachO upper/lower16 relocationsMartin Storsjo2017-07-132-0/+4
| | | | | | | | | | All other code in MachODump.cpp uses the same comparison, ((r_length & 0x1) == 1), for distinguishing between the two, while the code in llvm-objdump.cpp seemed to be incorrect. Differential Revision: https://reviews.llvm.org/D35240 llvm-svn: 307882
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-132-0/+41
| | | | | | | | | | | | | | | | | Summary: Add target hooks for printing and parsing target MMO flags. Targets may override getSerializableMachineMemOperandTargetFlags() to return a mapping from string to flag value for target MMO values that should be serialized/parsed in MIR output. Add implementation of this hook for AArch64 SuppressPair MMO flag. Reviewers: bogner, hfinkel, qcolombet, MatzeB Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34962 llvm-svn: 307877
* [sanstats] Remove a flaky test.Davide Italiano2017-07-132-4/+0
| | | | | | | | | I don't know a reliable way of crafting a test for this case, but I'll try a little harder. In the meanwhile, let's get the bots green again. Please note this will be tested by `check-cfi` once r307215 relands. llvm-svn: 307874
* [DWARF] Fixing a bug with processing of DWARF v5 indexed strings in Mach-O ↵Wolfgang Pieb2017-07-133-73/+276
| | | | | | | | | | | objects. Code to convert MachO - specific section debug section names to standard DWARF v5 section names was in the wrong place. Differential Revision: https://reviews.llvm.org/D35321 llvm-svn: 307872
* [sanstats] Print the correct line information.Davide Italiano2017-07-132-0/+4
| | | | | | | | The instrumentation tracks the return address and not that of the call so we remove one to compensate. Thanks for Peter Collingbourne for confirming the analysis of the problem. llvm-svn: 307871
* [CodeGenPrepare] Don't create dead instructions in addrmode sinkingEli Friedman2017-07-121-0/+24
| | | | | | | | | | When we fail to sink an instruction, we must make sure not to modify the function; otherwise, we end up in an infinite loop because CodeGenPrepare iterates until it doesn't make any changes. Fixes https://bugs.llvm.org/show_bug.cgi?id=33608 . llvm-svn: 307866
* [PGO] Enhance pgo counter promotionXinliang David Li2017-07-123-4/+169
| | | | | | | | | | | | | | | | | | | | | | | This is an incremental change to the promotion feature. There are two problems with the current behavior: 1) loops with multiple exiting blocks are totally disabled 2) a counter update can only be promoted one level up in the loop nest -- which does help much for short trip count inner loops inside a high trip-count outer loops. Due to this limitation, we still saw very large profile count fluctuations from run to run for the affected loops which are usually very hot. This patch adds the support for promotion counters iteratively across the loop nest. It also turns on the promotion for loops with multiple exiting blocks (with a limit). For single-threaded applications, the performance impact is flat on average. For instance, dealII improves, but povray regresses. llvm-svn: 307863
* AMDGPU: Fix converting unanalyzable global loads to SMRDMatt Arsenault2017-07-121-0/+20
| | | | | | | Not all memory dependence queries succeed, so this needs to be conservative if it fails. llvm-svn: 307861
* [x86] add select-of-constant tests; NFCSanjay Patel2017-07-121-4/+109
| | | | | | We're using cmov in these cases, but we could reduce to simpler ops. llvm-svn: 307859
* Add element atomic memset intrinsicDaniel Neilson2017-07-122-0/+79
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
* [AMDGPU] fcanonicalize elimination optimizationStanislav Mekhanoshin2017-07-121-0/+487
| | | | | | | | | | | | We are using multiplication by 1.0 to flush denormals and quiet sNaNs. That is possible to omit this multiplication if source of the fcanonicalize instruction is known to be flushed/quieted, i.e. if it comes from another instruction known to do the normalization and we are using IEEE mode to quiet sNaNs. Differential Revision: https://reviews.llvm.org/D35218 llvm-svn: 307848
* [LoopUnrollRuntime] NFC: Refactored safety checks of unrolling multi-exit loopAnna Thomas2017-07-121-0/+68
| | | | | | | | | | | Refactored the code and separated out a function `canSafelyUnrollMultiExitLoop` to reduce redundant checks and make it easier to add profitability heuristics later. Added tests to runtime unrolling to make sure that unrolling for multi-exit loops is not done unless the option -unroll-runtime-multi-exit is true. llvm-svn: 307843
* [LV] Don't allow outside uses of IVs if the SCEV is predicated on loop ↵Michael Kuperstein2017-07-121-0/+61
| | | | | | | | | conditions. This fixes PR33706. Differential Revision: https://reviews.llvm.org/D35227 llvm-svn: 307837
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-129-25/+196
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [LoopRotate] Fix DomTree update logic for unreachable nodes. Fix PR33701.Jakub Kuderski2017-07-121-0/+27
| | | | | | | | | | | | | | | | | | | Summary: LoopRotate manually updates the DoomTree by iterating over all predecessors of a basic block and computing the Nearest Common Dominator. When a predecessor happens to be unreachable, `DT.findNearestCommonDominator` returns nullptr. This patch teaches LoopRotate to handle this case and fixes [[ https://bugs.llvm.org/show_bug.cgi?id=33701 | PR33701 ]]. In the future, LoopRotate should be taught to use the new incremental API for updating the DomTree. Reviewers: dberlin, davide, uabelho, grosser Subscribers: efriedma, mzolotukhin Differential Revision: https://reviews.llvm.org/D35074 llvm-svn: 307828
* [x86] improve SBB optimizations for SETB/SETA with subtractSanjay Patel2017-07-121-5/+2
| | | | | | | | | | | | | | This is another step towards removing a combine that turns sext into select of constants and preparing the backend for an IR future where select is the canonical form. Earlier commits in this area: https://reviews.llvm.org/rL306040 https://reviews.llvm.org/rL306072 https://reviews.llvm.org/rL307404 (https://reviews.llvm.org/D34652) https://reviews.llvm.org/rL307471 llvm-svn: 307821
* [x86] add tests for improving sbb transforms; NFCSanjay Patel2017-07-121-0/+35
| | | | | | We're subtracting X from X the hard way... llvm-svn: 307819
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+30
| | | | | | | | A generic variant of IMPLICIT_DEF was added in r306875, but this survives to selection and hits a `Cannot Select`. Add handling that converts the note to a regular IMPLICIT_DEF. llvm-svn: 307817
* Add a test for r307754George Burgess IV2017-07-121-0/+16
| | | | | | | | | | | As promised in D35003. Uses -codegenprepare instead of -instcombine since we hit the same buggy path anyway, and CGP lets us keep this test really simple (instcombine likes turning the alloca T, N into alloca [N x T], which hides the bug this is testing for). llvm-svn: 307811
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-123-1/+9
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* Add back a CHECK line.Rafael Espindola2017-07-121-0/+1
| | | | | | | | I accidentally removed it in r307730. Thanks to Martin Storsjö for noticing! llvm-svn: 307801
* [CodeGen] Add dependency printerEvandro Menezes2017-07-1212-52/+52
| | | | | | | | Add SDep printer to make debugging sessions more productive. Differential revision: https://reviews.llvm.org/D35144 llvm-svn: 307799
* [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats.Davide Italiano2017-07-121-0/+15
| | | | | | | | | | FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797
* Add element atomic memmove intrinsicDaniel Neilson2017-07-122-0/+87
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-0/+19
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [X86][SSE] Fix file check prefix warning breaking buildbotsSimon Pilgrim2017-07-122-4/+4
| | | | llvm-svn: 307790
* Make shell redirection construct portableKamil Rytarowski2017-07-1222-23/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: NetBSD shell sh(1) does not support ">& /dev/null" construct. This is bashism. The portable and POSIX solution is to use: "> /dev/null 2>&1". This change fixes 22 Unexpected Failures on NetBSD/amd64 for the "check-llvm" target. Sponsored by <The NetBSD Foundation> Reviewers: joerg, dim, rnk Reviewed By: joerg, rnk Subscribers: rnk, davide, llvm-commits Differential Revision: https://reviews.llvm.org/D35277 llvm-svn: 307789
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-9/+13
| | | | | | | | | When we have a diamond ifcvt the fallthough block will have a branch at the end of it that disappears when predicated, so discount it from the predication cost. Differential Revision: https://reviews.llvm.org/D34952 llvm-svn: 307788
* [X86][SSE] Add 512-bit (iX bitcast(vXi1)) test casesSimon Pilgrim2017-07-122-0/+3245
| | | | | | Improves test coverage for pre-AVX512 targets as well llvm-svn: 307783
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-124-0/+25
| | | | llvm-svn: 307779
* [Linker] Add directives to support mixing ARM/Thumb module-level inline asm.Florian Hahn2017-07-122-0/+23
| | | | | | | | | | | | | | | | | | | | | | Summary: By prepending `.text .thumb .balign 2` to the module-level inline assembly from a Thumb module, the assembler will generate the assembly from that module as Thumb, even if the destination module uses an ARM triple. Similar directives are used for module-level inline assembly in ARM modules. The alignment and instruction set are reset based on the target triple before emitting the first function label. Reviewers: olista01, tejohnson, echristo, t.p.northover, rafael Reviewed By: echristo Subscribers: aemerson, javed.absar, eraman, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34622 llvm-svn: 307772
* [ARM] GlobalISel: Select s64 G_FCMPDiana Picus2017-07-121-0/+605
| | | | | | | Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. llvm-svn: 307763
* [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess.Michael Zuckerman2017-07-121-83/+143
| | | | | | Adding base test for AVX512 llvm-svn: 307761
* Specify complete target triple in testMatthias Braun2017-07-121-2/+2
| | | | | | This should fix the problems on the greendragon build. llvm-svn: 307747
* LowerTypeTests: When importing functions skip definitions where the summary ↵Peter Collingbourne2017-07-122-0/+8
| | | | | | | | | | | | | | contains a decl. This normally indicates mixed CFI + non-CFI compilation, and will result in us treating the function in the same way as a function defined outside of the LTO unit. Part of PR33752. Differential Revision: https://reviews.llvm.org/D35281 llvm-svn: 307744
* [WebAssembly] Expose the offset of each data segmentSam Clegg2017-07-123-4/+7
| | | | | | | | | | | | | | Summary: This allows tools like lld that process relocations to apply data relocation correctly. This information is required because relocation are stored as section offset. Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D35234 llvm-svn: 307741
* [codeview] Change readobj symbol dumping formatReid Kleckner2017-07-1131-164/+172
| | | | | | | | Avoid duplicating DictScope with hand-written names everywhere. Print the S_-prefixed symbol kind for every record. This should make it easier to search for certain kinds of records when debugging PDB linking. llvm-svn: 307732
* Fully fix the movw/movt addend.Rafael Espindola2017-07-111-1/+12
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [IPO] Temporarily rollback r307215.Davide Italiano2017-07-111-17/+0
| | | | | | | | | [GlobalOpt] Remove unreachable blocks before optimizing a function. While the change is presumably correct, it exposes a latent bug in DI which breaks on of the CFI checks. I'll analyze it further and try to understand what's going on. llvm-svn: 307729
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-1125-423/+590
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 introduces the notion of memory scopes in atomic operations to global and local memory. These scopes restrict how synchronization is achieved, which can result in improved performance. This change extends existing notion of synchronization scopes in LLVM to support arbitrary scopes expressed as target-specific strings, in addition to the already defined scopes (single thread, system). The LLVM IR and MIR syntax for expressing synchronization scopes has changed to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this replaces *singlethread* keyword), or a target-specific name. As before, if the scope is not specified, it defaults to CrossThread/System scope. Implementation details: - Mapping from synchronization scope name/string to synchronization scope id is stored in LLVM context; - CrossThread/System and SingleThread scopes are pre-defined to efficiently check for known scopes without comparing strings; - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in the bitcode. Differential Revision: https://reviews.llvm.org/D21723 llvm-svn: 307722
* [x86] auto-generate full checks; NFCSanjay Patel2017-07-111-79/+126
| | | | llvm-svn: 307718
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+36
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
* [ProfileData] Add new option to dump topn hottest functionsXinliang David Li2017-07-111-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D35155 llvm-svn: 307702
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