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* Disable flaky tests till they get fixed.Galina Kistanova2018-04-102-1/+2
| | | | llvm-svn: 329763
* [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.Geoff Berry2018-04-101-0/+25
| | | | | | | | | | | | | | | | Summary: When inserting MOVs to avoid Falkor HWPF collisions, the non-base register operand of load instructions (e.g. a register offset) was not being considered live, so it could potentially have been used as a scratch register, clobbering the actual offset value. Reviewers: mcrosier Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45502 llvm-svn: 329761
* [CVP] simplify phi with constant incoming values that match common variable ↵Sanjay Patel2018-04-101-0/+94
| | | | | | | | | | | | | | | | | | | | | | | edge values This is based on an example that was recently posted on llvm-dev: void *propagate_null(void* b, int* g) { if (!b) { return 0; } (*g)++; return b; } https://godbolt.org/g/xYk3qG The original code or constant propagation in other passes has obscured the fact that the phi can be removed completely. Differential Revision: https://reviews.llvm.org/D45448 llvm-svn: 329755
* [MachO] Emit Weak ReadOnlyWithRel to ConstDataSectionSteven Wu2018-04-101-0/+5
| | | | | | | | | | | | | | | | | Summary: Darwin dynamic linker can handle weak symbols in ConstDataSection. ReadonReadOnlyWithRel symbols should be emitted in ConstDataSection instead of normal DataSection. rdar://problem/39298457 Reviewers: dexonsmith, kledzik Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45472 llvm-svn: 329752
* Recommit r329716 "Add missing nullptr check before getSection() to ↵Jessica Paquette2018-04-101-0/+10
| | | | | | | | | | | | | AArch64MachObjectWriter::recordRelocation" This commit fixes the bot failures that were coming up before with r329716. The fix was to move the check for "isInSection()" inside of the if condition and emit the error there instead of waiting to get past the unreachable statement. This should work in debug and release builds now. llvm-svn: 329746
* [AArch64] Fix isel failure when BUILD_PAIR nodes are left over.Amara Emerson2018-04-101-0/+13
| | | | | | rdar://39175175 llvm-svn: 329743
* [X86] Split up -march=icelake to -client & -serverGabor Buella2018-04-105-5/+10
| | | | | | | | | | Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45055 llvm-svn: 329742
* Revert 329716 "Add missing nullptr check before getSection() to ↵Jessica Paquette2018-04-101-10/+0
| | | | | | | | AArch64MachObjectWriter::recordRelocation" This broke a bunch of bots so I'm reverting while I figure it out. llvm-svn: 329728
* Fix test failure in arm64-no-section.llJessica Paquette2018-04-101-2/+2
| | | | | | There was a missing not line. Also, tail call before ret -> call before ret. llvm-svn: 329723
* [CodeGen] Fix printing bundles in MIR outputKrzysztof Parzyszek2018-04-101-2/+1
| | | | | | | | | | | | | | | | Delay printing the newline until after the opening bracket was printed, e.g. BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 { renamable $r1 = S2_asr_i_r renamable $r1, 1 renamable $r21 = A2_tfrsi 0 } instead of BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 { renamable $r1 = S2_asr_i_r renamable $r1, 1 renamable $r21 = A2_tfrsi 0 } llvm-svn: 329719
* Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF."Peter Collingbourne2018-04-1011-191/+127
| | | | | | Caused a build failure in check-tsan. llvm-svn: 329718
* Add missing nullptr check to AArch64MachObjectWriter::recordRelocationJessica Paquette2018-04-101-0/+10
| | | | | | | | | | | There was missing nullptr check before a call to getSection() in recordRelocation. This would result in a segfault in code like the attached test. This adds the missing check and a test which makes sure we get the expected error output. llvm-svn: 329716
* [llvm-mca] Move the logic that prints dispatch unit statistics from ↵Andrea Di Biagio2018-04-105-5/+5
| | | | | | | | | | | BackendStatistics to its own view. This patch moves the logic that collects and analyzes dispatch events to the DispatchStatistics view. Added flag -dispatch-stats to print statistics related to the dispatch logic. llvm-svn: 329708
* [pdbutil] Print the checksum hex string when using the '-lines' optionAaron Smith2018-04-101-0/+5
| | | | llvm-svn: 329707
* [CodeGen/Dwarf] Rename the "sizetype" synthetic type and add it to the ↵Pavel Labath2018-04-105-11/+49
| | | | | | | | | | | | | | | | | | | | | | | | accelerator table Summary: This type is created on-demand and used as the base type for array ranges. Since it is "special", its construction did not go through the createTypeDIE function and so it was never inserted into the accelerator table, although it clearly belongs there. I add an explicit addAccelType call to insert it into the table. During review, we also decided to rename the type to something more unique to avoid confusion in case the user has own "sizetype" type. The new name for the type size __ARRAY_SIZE_TYPE__. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45445 llvm-svn: 329705
* [llvm-mca] Increase the default number of iterations to 100.Andrea Di Biagio2018-04-104-55/+144
| | | | llvm-svn: 329694
* [DA] Improve alias checking in dependence analysisDavid Green2018-04-101-0/+140
| | | | | | | | | | | | Improve the alias analysis to account for cases where we know that src/dst pairs cannot alias due to things like TBAA. As we know they are noalias, we know no dependency can occur. Also fixes issues around the size parameter to AA being incorrect. Differential Revision: https://reviews.llvm.org/D42381 llvm-svn: 329692
* [AArch64] Use FP to access the emergency spill slotFrancis Visoiu Mistrih2018-04-102-2/+23
| | | | | | | | | | | | | | | | | | | | | In the presence of variable-sized stack objects, we always picked the base pointer when resolving frame indices if it was available. This makes us hit an assert where we can't reach the emergency spill slot if it's too far away from the base pointer. Since on AArch64 we decide to place the emergency spill slot at the top of the frame, it makes more sense to use FP to access it. The changes here don't affect only emergency spill slots but all the frame indices. The goal here is to try to choose between FP, BP and SP so that we minimize the offset and avoid scavenging, or worse, asserting when trying to access a slot allocated by the scavenger. Previously discussed here: https://reviews.llvm.org/D40876. Differential Revision: https://reviews.llvm.org/D45358 llvm-svn: 329691
* [AMDGPU] For OS type AMDPAL, fixed scratch on compute shaderTim Renouf2018-04-101-0/+29
| | | | | | | | | | | | | | | | | | | | | Summary: For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders). This commit fixes that to use offset 0x10 instead of offset 0 for a compute shader, per the PAL ABI spec. V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading scratch descriptor from GIT. Reviewers: kzhuravl, nhaehnle, timcorringham Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm Differential Revision: https://reviews.llvm.org/D44468 Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f llvm-svn: 329690
* AArch64: diagnose unpredictable store-exclusive instructionsTim Northover2018-04-102-8/+69
| | | | | | | | Much like any written register in load/store instructions, the status register is not allowed to overlap with any others. So diagnose it like we already do with the other cases. llvm-svn: 329687
* [llvm-ar] Temporarily make the tool case detection test Windows-only to fix ↵Alexandre Ganea2018-04-101-0/+1
| | | | | | the build (introduced in r329658) llvm-svn: 329683
* [AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by ↵Sander de Smalen2018-04-104-0/+194
| | | | | | | | | | | | | | immediate) instructions. Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro Reviewed By: rengolin, fhahn Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45371 llvm-svn: 329681
* Reapply "[llvm-mca] Do not separate iterations with a newline in the ↵Andrea Di Biagio2018-04-109-30/+30
| | | | | | | | timeline view." This reapplies r329403 with a fix for the floating point rounding issue. llvm-svn: 329680
* [AArch64][SVE] Asm: Add support for SVE INDEX instructions.Sander de Smalen2018-04-102-0/+272
| | | | | | | | | | | | Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro Reviewed By: rengolin, fhahn Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45370 llvm-svn: 329674
* [x86] Model the direction flag (DF) separately from the rest of EFLAGS.Chandler Carruth2018-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 llvm-svn: 329673
* [X86] Prevent folding loads with 64-bit ANDs with immediates that fit in ↵Craig Topper2018-04-101-0/+31
| | | | | | | | | | | | 32-bits. Prefer to use the 32-bit AND with immediate instead. Primarily I'm doing this to ensure that immediates created by shrinkAndImmediate will always get absorbed into the AND. But I do believe this would be a reduction in the number of uops that need to execute. Ideally we should shrink the 'and' and the 'load' during DAG combine to re-enable the fold. Fixes PR37063. llvm-svn: 329667
* [SSAUpdaterBulk] Handle CFG with unreachable from entry blocks.Michael Zolotukhin2018-04-101-0/+26
| | | | llvm-svn: 329660
* [llvm-ar] Fix lib.exe detection when running within MSVC toolchainAlexandre Ganea2018-04-101-0/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D44808 llvm-svn: 329658
* [x86] Introduce a pass to begin more systematically fixing PR36028 and ↵Chandler Carruth2018-04-1012-3691/+3690
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 llvm-svn: 329657
* ShadowCallStack/x86_64: Ignore pseudo-machine instructionsVlad Tsyrklevich2018-04-101-0/+8
| | | | llvm-svn: 329656
* Object: Don't mark alias unconditionally definedVitaly Buka2018-04-101-2/+4
| | | | | | | | | | | | | | Summary: Can't remove EmitAssignment override as llvm/test/Object/X86/nm-bitcodeweak.test expects this behavior. Reviewers: pcc, espindola Subscribers: mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D44596 llvm-svn: 329651
* [X86] Added missing AAD/AAM immediate schedule testsSimon Pilgrim2018-04-092-6/+62
| | | | | | Added some more TODOs for missing instructions llvm-svn: 329626
* [MemorySSAUpdater] Mark Phi users of a node being moved as non-optimizeZhaoshi Zheng2018-04-091-0/+34
| | | | | | | | | | Fix PR36484, as suggested: <quote> during moves, mark the direct users of the erased things that were phis as "not to be optimized" <quote> llvm-svn: 329621
* AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel headerKonstantin Zhuravlyov2018-04-092-5/+2
| | | | | | | | | | | 1. Remove max_scratch_backing_memory_byte_size from kernel header 2. Make it a reserved field 3. Ignore it while parsing assembly for backwards compatibility 4. Bump up minor version of kernel header Differential Revision: https://reviews.llvm.org/D45452 llvm-svn: 329620
* [X86] Don't use Lower512IntUnary to split bitcasts with v32i16/v64i8 types ↵Craig Topper2018-04-091-0/+22
| | | | | | | | | | | | | | on targets without AVX512BW. LowerIntUnary as its name says has an assert for integer types. But for the bitcast case one side might be an FP type. Rather than making sure the function really works for fp types and renaming it. Just do really basic splitting directly. The LowerIntUnary has the advantage that it can peek through BUILD_VECTOR because every other call is during Lowering. But these calls are during legalization and will be followed by a DAG combine round. Revert some change to LowerVectorIntUnary that were originally made just to make these two calls work even in pure integer cases. This was found purely by compiling the avx512f-builtins.c test from clang so I've copied over the offending function from that. llvm-svn: 329616
* [Debuginfo][COFF] Minimal serialization support for precompiled types recordsAlexandre Ganea2018-04-093-0/+57
| | | | | | | | | | | | | This change adds support for the LF_PRECOMP and LF_ENDPRECOMP records required to read/write Microsoft precompiled types .objs. See https://en.wikipedia.org/wiki/Precompiled_header#Microsoft_Visual_C_and_C++ This also adds handling for the .debug$P section, which is actually a .debug$T section in disguise, found only in precompiled .objs. Differential Revision: https://reviews.llvm.org/D45283 llvm-svn: 329613
* AArch64: Allow offsets to be folded into addresses with ELF.Peter Collingbourne2018-04-0911-127/+191
| | | | | | | | | | | | | | | This is a code size win in code that takes offseted addresses frequently, such as C++ constructors that typically need to compute an offseted address of a vtable. It reduces the size of Chromium for Android's .text section by 46KB, or 56KB with ThinLTO (which exposes more opportunities to use a direct access rather than a GOT access). Because the addend range is limited in COFF and Mach-O, this is enabled for ELF only. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 329611
* Revert "AMDGPU: enable 128-bit for local addr space under an option"Alex Shlyapnikov2018-04-096-14/+14
| | | | | | | | | | | | | | This reverts commit r329591. It breaks various bots: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/16516 http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/17374 http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/15992 http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/11251 ... llvm-svn: 329610
* [X86] Remove GCCBuiltin name from pmuldq/pmuludq intrinsics so clang can ↵Craig Topper2018-04-095-14/+383
| | | | | | | | | | custom lower to native IR. Update fast-isel intrinsic tests for clang's new codegen. In somes cases fast-isel fails to remove the and/shifts and uses blends or conditional moves. But once masking gets involved, fast-isel aborts on the mask portion and we DAG combine more thorougly. llvm-svn: 329604
* [SLP] Additional tests for reorder reuse vectorization, NFC.Alexey Bataev2018-04-091-0/+230
| | | | llvm-svn: 329603
* [X86] Revert the SLM part of r328914.Craig Topper2018-04-092-22/+24
| | | | | | While it appears to be correct information based on Intel's optimization manual and Agner's data, it causes perf regressions on a couple of the benchmarks in our internal list. llvm-svn: 329593
* AMDGPU: enable 128-bit for local addr space under an optionMarek Olsak2018-04-096-14/+14
| | | | | | | | | | | | | | | | | Author: Samuel Pitoiset ds_read_b128 and ds_write_b128 have been recently enabled under the amdgpu-ds128 option because the performance benefit is unclear. Though, using 128-bit loads/stores for the local address space appears to introduce regressions in tessellation shaders. Not sure what is broken, but as ds_read_b128/ds_write_b128 are not enabled by default, just introduce a global option and enable 128-bit only if requested (until it's fixed/used correctly). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 llvm-svn: 329591
* [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)Andrea Di Biagio2018-04-097-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to parse code comments in search for special "markers" used to select regions of code. Example: # LLVM-MCA-BEGIN My Code Region .... # LLVM-MCA-END The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an AsmCommentConsumer) the parsing of code comments to search for begin/end code region markers. A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new region of code. A comment starting with substring "LLVM-MCA-END" marks the end of the last region. This implementation doesn't allow regions to overlap. Each region can have a optional description; internally, each region is identified by a range of source code locations (SMLoc). MCInst objects are added to a region R only if the source location for the MCInst is in the range of locations specified by R. By default, the tool allocates an implicit "Default" code region which contains every source location. See new tests llvm-mca-marker-*.s for a few examples. A new Backend object is created for every region. So, the analysis is conducted on every parsed code region. The final report is the union of the reports generated for every code region. Note that empty regions are skipped. Special "[#] Code Region - ..." strings are used in the report to mark the portion which is specific to a code region only. For example, see llvm-mca-markers-5.s. Differential Revision: https://reviews.llvm.org/D45433 llvm-svn: 329590
* [X86][SSE] Add floating point add/mul strict (ordered) vector.reduce tests ↵Simon Pilgrim2018-04-092-0/+3523
| | | | | | (PR36732) llvm-svn: 329587
* Support generic expansion of ordered vector reduction (PR36732)Simon Pilgrim2018-04-091-8/+36
| | | | | | | | | | Without the fast math flags, the llvm.experimental.vector.reduce.fadd/fmul intrinsic expansions must be expanded in order. This patch scalarizes the reduction, applying the accumulator at the start of the sequence: ((((Acc + Scl[0]) + Scl[1]) + Scl[2]) + ) ... + Scl[NumElts-1] Differential Revision: https://reviews.llvm.org/D45366 llvm-svn: 329585
* [llvm-cov] Implement -ignore-filename-regex= option for excluding source files.Max Moroz2018-04-091-0/+71
| | | | | | | | | | | | | | | | | | | Summary: The option is helpful for large projects where it's not feasible to specify sources which user would like to see in the report. Instead, it allows to black-list specific sources via regular expressions (e.g. now it's possible to skip all files that have "test" in its name). This also partially fixes https://bugs.llvm.org/show_bug.cgi?id=34277 Reviewers: vsk, morehouse, liaoyuke Reviewed By: vsk Subscribers: kcc, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D43907 llvm-svn: 329581
* [MachineLICM] Re-enable hoisting of constant storesZaara Syeda2018-04-091-0/+145
| | | | | | | | | | | | This patch fixes an issue exposed on the SystemZ build bots when committing https://reviews.llvm.org/rL327856. The hoisting was temporarily disabled with an option. This patch now re-enables hoisting and checks that we only hoist a store instruction when all its operands are either constant caller preserved registers or immediates. Differential Revision: https://reviews.llvm.org/D45286 llvm-svn: 329577
* [CodeGen/AccelTable] Don't emit zero-CU name indexesPavel Labath2018-04-091-0/+19
| | | | | | | | | | | | | | | | | Summary: If an input DICompileUnit is completely empty (e.g., the result of running "clang -g" on an empty file), we don't bother emitting an empty DWARF CU. When we do that, we must make sure we don't also emit a DWARF v5 name index, as DWARF specifies that each index must reference at least one compilation unit. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45435 llvm-svn: 329575
* [RuntimeDyld][PowerPC] Fix a newly added test in r329355Krasimir Georgiev2018-04-091-1/+1
| | | | | | | | | | | | | | Summary: The bit widths are wrong. Reviewers: bkramer, lhames, hans Reviewed By: hans Subscribers: hans, nemanjai, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D45361 llvm-svn: 329573
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the ↵Hans Wennborg2018-04-099-30/+30
| | | | | | | | | | | | timeline view." This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251 > Also, update a few tests to minimize the diff in D45369. > No functional change intended. llvm-svn: 329569
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