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* InstCombine: fold (sitofp (zext x)) to (uitofp x)Fiona Glaser2015-04-211-0/+9
| | | | | | | This is okay because the zext guarantees the high bit is zero, and so the value is unsigned. llvm-svn: 235364
* Fix flakiness in fp16-promote.llPirama Arumuga Nainar2015-04-201-578/+194
| | | | | | | | | | | | | | | | | | | | | | | Summary: In the f16-promote test, make the checks for native conversion instructions similar to the libcall checks: - Remove hard coded register names - Do not check exact instruction sequences. This fixes test flakiness due to non-determinism in instruction scheduling and register allocation. I also fixed a few minor things in the CHECK-LIBCALL checks. I'll try to find a way to check that unnecessary loads, stores, or conversions don't happen. Reviewers: mzolotukhin, srhines, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9112 llvm-svn: 235363
* bugpoint Enhancement.JF Bastien2015-04-201-0/+17
| | | | | | | | | | | | | | | | | | | Summary: This patch adds two flags to `bugpoint`: "-replace-funcs-with-null" and "-disable-pass-list-reduction". When "-replace-funcs-with-null" is specified, bugpoint will, instead of simply deleting function bodies, replace all uses of functions and then will delete functions completely from the test module, correctly handling aliasing and @llvm.used && @llvm.compiler.used. This part was conceived while trying to debug the PNaCl IR simplification passes, which don't allow undefined functions (ie no declarations). With "-disable-pass-list-reduction", bugpoint won't try to reduce the set of passes causing the "crash". This is needed in cases where one is trying to debug an issue inside the PNaCl IR simplification passes which is causing an PNaCl ABI verification error, for example. Reviewers: jfb Reviewed By: jfb Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D8555 llvm-svn: 235362
* use update_llc_test_checks.py to tighten checkingSanjay Patel2015-04-201-13/+22
| | | | | | | Also, replace win and linux runs with a generic run because that makes no difference in what this test is checking. llvm-svn: 235361
* [WinEH] Fix problem with mapping shared empty handler blocks.Andrew Kaylor2015-04-201-0/+110
| | | | | | Differential Revision: http://reviews.llvm.org/D9125 llvm-svn: 235354
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-202-31/+187
| | | | llvm-svn: 235344
* Fixing line endingsAndrew Kaylor2015-04-201-14/+14
| | | | llvm-svn: 235342
* [MIPS] OperationAction for FP_TO_FP16, FP16_TO_FPPirama Arumuga Nainar2015-04-201-0/+96
| | | | | | | | | | | | | | | | | | | | | | Summary: Set operation action for FP16 conversion opcodes, so the Op legalizer can choose the gnu_* libcalls for Mips. Set LoadExtAction and TruncStoreAction for f16 scalars and vectors to prevent (fpext (load )) and (store (fptrunc)) from getting combined into unsupported operations. Added test cases to test that these operations are handled correctly for f16 scalars and vectors. This patch depends on http://reviews.llvm.org/D8755. Reviewers: srhines Subscribers: llvm-commits, ab Differential Revision: http://reviews.llvm.org/D8804 llvm-svn: 235341
* DAGCombine: Remove redundant NaN checks around ISD::FSQRTTom Stellard2015-04-201-0/+50
| | | | | | | | This folds: (select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x) llvm-svn: 235333
* [mips][microMIPSr6] Implement BITSWAP instructionJozef Kolek2015-04-202-0/+4
| | | | | | | | Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
* [AArch64] LORID_EL1 register must be treated as read-onlyVladimir Sukharev2015-04-202-2/+58
| | | | | | | | | | | | Patch by: John Brawn Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9105 llvm-svn: 235314
* [InlineFunction] Don't add lifetime markers for zero-sized allocas.Akira Hatanaka2015-04-201-0/+24
| | | | | | | | | This commit fixes the code which adds lifetime markers in InlineFunction to skip zero-sized allocas instead of asserting on them. rdar://problem/20531155 llvm-svn: 235312
* Recognize n/1 in the SCEV divide functionBrendon Cahoon2015-04-201-0/+70
| | | | | | | | | | | | n/1 generates a quotient equal to n and a remainder of 0. If this case is not recognized, then the SCEV divide() function can return a remainder that is greater than or equal to the denominator, which means the delinearized subscripts for the test case will be incorrect. Differential Revision: http://reviews.llvm.org/D9003 llvm-svn: 235311
* [mips][microMIPSr6] Implement disassembler supportJozef Kolek2015-04-201-0/+7
| | | | | | | | Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
* [mips][microMIPSr6] Implement BALC and BC instructionsJozef Kolek2015-04-201-0/+5
| | | | | | | | This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
* Look past locals in comdats.Rafael Espindola2015-04-201-0/+2
| | | | | | | | | | | We have to avoid converting a reference to a global into a reference to a local, but it is fine to look past a local. Patch by Vasileios Kalintiris. I just moved the comment and added thet test. llvm-svn: 235300
* [X86][FastIsel] Fix assertion failure when selecting int-to-double ↵Andrea Di Biagio2015-04-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | conversion (PR23273). This fixes a regression introduced at revision 231243. The target-independent selection algorithm in FastISel knows how to select a SINT_TO_FP if the target is SSE but not AVX. That is because on X86, the tablegen'd 'fastEmit' functions know how to select CVTSI2SSrr and CVTSI2SDrr. Method X86FastISel::X86SelectSIToFP was therefore working under the wrong assumption that the target was AVX. That assumption was incorrect since we can have a target that is neither AVX nor SSE. So, rather than asserting for the presence of AVX, we should have had an early exit from 'X86SelectSIToFP' if the target was not AVX. This patch fixes the issue replacing the invalid assertion with an early exit. Thanks to Dimitry Andric for reporting this problem and for providing a small reproducible testcase. Added test pr23273.ll. llvm-svn: 235295
* [Mips] Support DT_MIPS_OPTIONS dynamic section tag in the llvm-readobjSimon Atanasyan2015-04-202-0/+22
| | | | llvm-svn: 235285
* [InlineAsm] Remove EarlyClobber on registers that are also inputsHal Finkel2015-04-201-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an inline asm call has an output register marked as early-clobber, but that same register is also an input operand, what should we do? GCC accepts this, and is documented to accept this for read/write operands saying, "Furthermore, if the earlyclobber operand is also a read/write operand, then that operand is written only after it's used." For write-only operands, the situation seems less clear, but I have at least one existing codebase that assumes this will work, in part because it has syscall macros like this: ({ \ register uint64_t r0 __asm__ ("r0") = (__NR_ ## name); \ register uint64_t r3 __asm__ ("r3") = ((uint64_t) (arg0)); \ register uint64_t r4 __asm__ ("r4") = ((uint64_t) (arg1)); \ register uint64_t r5 __asm__ ("r5") = ((uint64_t) (arg2)); \ __asm__ __volatile__ \ ("sc" \ : "=&r"(r0),"=&r"(r3),"=&r"(r4),"=&r"(r5) \ : "0"(r0), "1"(r3), "2"(r4), "3"(r5) \ : "r6","r7","r8","r9","r10","r11","r12","cr0","memory"); \ r3; \ }) Furthermore, with register aliases and subregister relationships that only the backend knows about, rejecting this in the frontend seems like a difficult proposition (if we wanted to do so). However, keeping the early-clobber flag on the INLINEASM MI does not work for us, because it will cause the register's live interval to end to soon (so it will not appear defined to be used as an input). Fortunately, fixing this does not seem hard: When forming the INLINEASM MI, check to see if any of the early-clobber outputs are also inputs, and if so, remove the early-clobber flag. llvm-svn: 235283
* [X86][SSE] Fix for getScalarValueForVectorElement to detect scalar sources ↵Simon Pilgrim2015-04-191-0/+16
| | | | | | | | | | requiring truncation. The fix ensures that scalar sources inserted into a vector are the correct bit size. Integer scalar sources from BUILD_VECTOR and SCALAR_TO_VECTOR nodes may require truncation that this function doesn't currently support. llvm-svn: 235281
* [X86][SSE] Extended copysign tests to include llvm intrinsic implementation ↵Simon Pilgrim2015-04-191-7/+125
| | | | | | and constant folding. llvm-svn: 235279
* [MemCpyOpt] Don't force i64 when promoting memset/memcpy sizes.Ahmed Bougacha2015-04-181-0/+32
| | | | | | | | | | Harden r235258 to support any integer bitwidth. The quick glance at the reference made me think only i32 and i64 were valid types, but they're not special, so any overload is legal. Thanks to David Majnemer for noticing! llvm-svn: 235261
* [X86][AVX2] Force execution domain on broadcast folding tests.Simon Pilgrim2015-04-181-3/+9
| | | | llvm-svn: 235260
* [X86][SSE] Force execution domain on float/double unpack shuffle tests.Simon Pilgrim2015-04-182-12/+36
| | | | llvm-svn: 235259
* [MemCpyOpt] Promote both memset/memcpy sizes if differently typed.Ahmed Bougacha2015-04-181-3/+35
| | | | | | | | | | | | | Followup to r235232, which caused PR23278. We can't assume the memset and memcpy sizes have the same type, as nothing in the language reference prevents that. Instead, zext both to i64 if they disagree. While there, robustify tests by using i8 %c rather than i8 0 for the memset character. llvm-svn: 235258
* [InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31)David Majnemer2015-04-181-0/+16
| | | | | | | Multiplying INT_MIN by 1 doesn't trigger nsw. However, shifting 1 into the sign bit *does* trigger nsw. llvm-svn: 235250
* [GlobalMerge] Look at uses to create smaller global sets.Ahmed Bougacha2015-04-188-8/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of merging everything together, look at the users of GlobalVariables, and try to group them by function, to create sets of globals used "together". Using that information, a less-aggressive alternative is to keep merging everything together *except* globals that are only ever used alone, that is, those for which it's clearly non-profitable to merge with others. In my testing, grouping by Function is too aggressive, but grouping by BasicBlock is too conservative. Anything in-between isn't trivially available, so stick with Function grouping for now. cl::opts are added for testing; both enabled by default. A few of the testcases aren't testing the merging proper, but just various edge cases when merging does occur. Update them to use the previous grouping behavior. Also, one of the tests is unrelated to GlobalMerge; change it accordingly. While there, switch to r234666' flags rather than the brutal -O3. Differential Revision: http://reviews.llvm.org/D8070 llvm-svn: 235249
* [AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.Ahmed Bougacha2015-04-171-0/+22
| | | | | | | | | | | | | | | | | | | The result is either an Untyped reg sequence, on ldN with N > 1, or just the type of the input vector, on ld1. Don't force Untyped. Instead, just use the type of the reg sequence. This mirrors the behavior of createTuple, which feeds the LD1*_POST. The narrow code path wasn't actually covered by tests, because V64 insert_vector_elt are widened to V128 before the LD1LANEpost combine has the chance to run, usually. The only case where it does run on V64 vectors is if the vector ops legalizer ran. So, tickle the code with a ctpop. Fixes PR23265. llvm-svn: 235243
* Fix another typo in r235224 testcase. NFC.Ahmed Bougacha2015-04-171-9/+9
| | | | | | Third time's the charm! llvm-svn: 235242
* [WinEH] Fixes for a few cppeh failures.Andrew Kaylor2015-04-172-0/+537
| | | | | | Differential Review: http://reviews.llvm.org/D9065 llvm-svn: 235239
* [MemCpyOpt] Optimize double-storing by memset+memcpy.Ahmed Bougacha2015-04-171-0/+54
| | | | | | | | | | | | | | | | | | A common idiom in some code is to do the following: memset(dst, 0, dst_size); memcpy(dst, src, src_size); Some of the memset is redundant; instead, we can do: memcpy(dst, src, src_size); memset(dst + src_size, 0, dst_size <= src_size ? 0 : dst_size - src_size); Original patch by: Joel Jones Differential Revision: http://reviews.llvm.org/D498 llvm-svn: 235232
* AArch64: Add test for returning [2 x i64] in registers. NFC.Pete Cooper2015-04-171-0/+11
| | | | llvm-svn: 235228
* Compute A-B when A or B is weak.Rafael Espindola2015-04-172-12/+16
| | | | | | | | | | | | | | | | | | | | Similar to r235222, but for the weak symbol case. In an "ideal" assembler/object format an expression would always refer to the final value and A-B would only be computed from a section in the same comdat as A and B with A and B strong. Unfortunately that is not the case with debug info on ELF, so we need an heuristic. Since we need an heuristic, we may as well use the same one as gas: * call weak_sym : produces a relocation, even if in the same section. * A - weak_sym and weak_sym -A: don't produce a relocation if we can compute it. This fixes pr23272 and changes the fix of pr22815 to match what gas does. llvm-svn: 235227
* Fix typo in r235224 testcase. NFC.Ahmed Bougacha2015-04-171-1/+1
| | | | llvm-svn: 235226
* [AArch64] Avoid vector->load dependency cycles when creating LD1*post.Ahmed Bougacha2015-04-171-1/+22
| | | | | | | | They would break the SelectionDAG. Note that the opposite load->vector dependency is already obvious in: (LD1*post vec, ..) llvm-svn: 235224
* Compute A-B if both A and B are in the same comdat section.Rafael Espindola2015-04-171-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of pr23272. A small annoyance with the assembly syntax we implement is that given an expression there is no way to know if what is desired is the value of that expression for the symbols in this file or for the final values of those symbols in a link. The first case is useful for use in sections that get discarded or ignored if the section they are describing is discarded. For axample, consider A-B where A and B are in the same comdat section. We can compute the value of the difference in the section that is present in the current .o and if that section survives to the final DSO the value will still will be correct. But the section is in a comdat. Another section from another object file might be used istead. We know that that section will define A and B, but we have no idea what the value of A-B might be. In practice we have to assume that the intention is to compute the value in the current section since otherwise the is no way to create something like the debug aranges section. llvm-svn: 235222
* Add support to promote f16 to f32Pirama Arumuga Nainar2015-04-171-0/+1287
| | | | | | | | | | | | | | Summary: This patch adds legalization support to operate on FP16 as a load/store type and do operations on it as floats. Tests for ARM are added to test/CodeGen/ARM/fp16-promote.ll Reviewers: srhines, t.p.northover Differential Revision: http://reviews.llvm.org/D8755 llvm-svn: 235215
* [mips][FastISel] Implement FastMaterializeAlloca in Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+32
| | | | | | | | | | | | | | | | | | Summary: Implement the method FastMaterializeAlloca in Mips fast-isel Based on a patch by Reed Kotler. Test Plan: Passes test-suite at O0/O2 for mips32 r1/r2 fastalloca.ll Reviewers: dsanders, rkotler Subscribers: rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6742 llvm-svn: 235213
* [X86, AVX] add an exedepfix entry for vmovq == vmovlps == vmovlpdSanjay Patel2015-04-174-11/+6
| | | | | | | | | | This is the AVX extension of r235014: http://llvm.org/viewvc/llvm-project?view=revision&revision=235014 Review: http://reviews.llvm.org/D8691 llvm-svn: 235210
* Add support for v1i128 type.Kit Barton2015-04-171-1/+1
| | | | | | | | | | | | The v1i128 type is needed for the quadword add/substract instructions introduced in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128 are to be passed in a single vector register, while parameters of type i128 are passed in pairs of GPRs. Thus, it is necessary to be able to differentiate between v1i128 and i128 in LLVM. http://reviews.llvm.org/D8564 llvm-svn: 235198
* [mips][FastISel] Implement shift ops for Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+122
| | | | | | | | | | | | | | | | | | Summary: Add shift operators implementation to fast-isel for Mips. These are shift ops for non legal forms, i.e. i8 and i16. Based on a patch by Reed Kotler. Test Plan: Reviewers: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6726 llvm-svn: 235194
* Fix TRUNCATE splitting helper logic.James Molloy2015-04-171-0/+33
| | | | | | | | | This is a followon to r233681 - I'd misunderstood the semantics of FTRUNC, and had confused it with (FP_ROUND ..., 0). Thanks for Ahmed Bougacha for his post-commit review! llvm-svn: 235191
* [mips] Teach the delay slot filler to remove needless KILL instructions.Vasileios Kalintiris2015-04-171-0/+14
| | | | | | | | | | | | | | | | | | Summary: Previously, the presence of KILL instructions would block valid candidates from filling a specific delay slot. With the elimination of the KILL instructions, in the appropriate range, we are able to fill more slots and keep the information from future def/use analysis consistent. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D7724 llvm-svn: 235183
* Add a proper fix for pr23025.Rafael Espindola2015-04-171-0/+5
| | | | | | | Instead of avoiding looking past every global symbol, only do so if the symbol is in a comdat. llvm-svn: 235181
* Revert r235154-r235156, they cause asserts when building win64 code ↵Nico Weber2015-04-1711-281/+236
| | | | | | (http://crbug.com/477988) llvm-svn: 235170
* Add a reduced testcase from pr23025.Rafael Espindola2015-04-171-0/+18
| | | | llvm-svn: 235168
* Don't walk aliases from global to local symbols in comdats.Rafael Espindola2015-04-171-0/+18
| | | | | | This fixes pr23196. llvm-svn: 235167
* Write relocation sections contiguously.Rafael Espindola2015-04-174-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linkers normally read all the relocations upfront to compute the references between sections. Putting them together is a bit more cache friendly. I benchmarked linking a Release+Asserts clang with gold on a vm. I tried all 4 combinations of --gc-sections/no --gc-section hot and cold cache. I cleared the cache with echo 3 > /proc/sys/vm/drop_caches and warmed it up by running the link once before timing the subsequent ones. With cold cache and --gc-sections the time goes from 1.86130781665 +- 0.01713126697463843 seconds to 1.82370735105 +- 0.014127522318814516 seconds With cold cache and no --gc-sections the time goes from 1.6087245435500002 +- 0.012999066825178644 seconds to 1.5687122041500001 +- 0.013145850126026619 seconds With hot cache and no --gc-sections the time goes from 0.926200939 ( +- 0.33% ) seconds to 0.907200079 ( +- 0.31% ) seconds With hot cache and gc sections the time goes from 1.183038049 ( +- 0.34% ) seconds to 1.147355862 ( +- 0.39% ) seconds llvm-svn: 235165
* [opaque pointer type] Explicit pointee type for call instructionDavid Blaikie2015-04-173-0/+6
| | | | | | | | | | Use an extra bit in the CCInfo to flag the newer version of the instructiont hat includes the type explicitly. Tested the newer error cases I added, but didn't add tests for the finer granularity improvements to existing error paths. llvm-svn: 235160
* Fix test failure due to racing commitsReid Kleckner2015-04-172-4/+4
| | | | | | | It looks like r235145 changed the .ll syntax for variadic calls. Update tests to use the new syntax. llvm-svn: 235156
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