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* [x86] regenerate test checks; NFCSanjay Patel2018-01-151-4/+7
| | | | llvm-svn: 322519
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-153-37/+66
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-152-0/+152
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-151-0/+52
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
* Update BTVER2 sched numbers for some AVX instructions (xmm version).Andrew V. Tischenko2018-01-153-29/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D40067 llvm-svn: 322485
* Revert "[DAG] Elide overlapping stores"Benjamin Kramer2018-01-151-2/+3
| | | | | | | This reverts commit r322085. Internal PPC testing is still showing the same symptoms as when this patch landed the last time. llvm-svn: 322474
* [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV ↵Andrei Elovikov2018-01-151-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | from a trunc. Summary: This method is supposed to be called for IVs that have casts in their use-def chains that are completely ignored after vectorization under PSE. However, for truncates of such IVs the same InductionDescriptor is used during creation/widening of both original IV based on PHINode and new IV based on TruncInst. This leads to unintended second call to recordVectorLoopValueForInductionCast with a VectorLoopVal set to the newly created IV for a trunc and causes an assert due to attempt to store new information for already existing entry in the map. This is wrong and should not be done. Fixes PR35773. Reviewers: dorit, Ayal, mssimpso Reviewed By: dorit Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41913 llvm-svn: 322473
* [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 ↵Gadi Haber2018-01-152-0/+70464
| | | | | | | | | | | | | | | bits isa sets.<NFC> NFC. Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41172 Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39 llvm-svn: 322471
* [GlobalsAA] Don't let dbg intrinsics affect analysis resultMikael Holmen2018-01-151-0/+57
| | | | | | | | | | | | | | | | | | Summary: This fixes PR35899. Debug info intrinsics shouldn't affect code generation so ignore them in GlobalsAA. Reviewers: hfinkel, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D41984 llvm-svn: 322470
* [BasicAA] Stop crashing when dealing with pointers > 64 bits.Davide Italiano2018-01-151-0/+12
| | | | | | | | | | | | | | | An alternative (and probably better) fix would be that of making `Scale` an APInt, and there's a patch floating around to do this. As we're still discussing it, at least stop crashing in the meanwhile (added bonus, we now have a regression test for this situation). Fixes PR35843. Thanks to Eli for suggesting the fix and Simon for reporting and reducing the bug. llvm-svn: 322467
* [X86][SSE] Tag PR21137 test caseSimon Pilgrim2018-01-141-1/+2
| | | | | | The test was added ages ago, but we didn't comment where it came from. llvm-svn: 322465
* [X86] Add test cases for D41794.Craig Topper2018-01-142-0/+408
| | | | llvm-svn: 322464
* [X86][SSE] Add PR22391 test caseSimon Pilgrim2018-01-141-0/+45
| | | | llvm-svn: 322463
* [X86] Autoupgrade kunpck intrinsics using vector operations instead of ↵Craig Topper2018-01-144-72/+67
| | | | | | | | | | | | | | | | scalar operations Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free. Reviewers: spatel, RKSimon, zvi, jina.nahias Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42018 llvm-svn: 322462
* [X86] Regenerate fp128 testSimon Pilgrim2018-01-141-11/+18
| | | | llvm-svn: 322460
* [X86][SSE] Support combining MOVLHPS undef inputsSimon Pilgrim2018-01-141-2/+1
| | | | llvm-svn: 322459
* [X86][SSE] Add v2f64 3u shuffle testSimon Pilgrim2018-01-141-0/+14
| | | | | | Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask. llvm-svn: 322458
* [x86] auto-generate complete checks; NFCSanjay Patel2018-01-142-21/+73
| | | | llvm-svn: 322457
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output ↵Craig Topper2018-01-148-304/+15
| | | | | | types have the same number of elements. llvm-svn: 322455
* [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.Craig Topper2018-01-141-2/+2
| | | | | | | | We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements. Ideally we'd just use ISD::TRUNCATE for these cases instead. llvm-svn: 322454
* [X86] Improve legalization of vXi16/vXi8 selects.Craig Topper2018-01-144-68/+70
| | | | | | | | Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization. Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already. llvm-svn: 322450
* [X86] Add an avx512bw command line to the avx512-vec-cmp.ll test. Add some ↵Craig Topper2018-01-141-143/+283
| | | | | | | | additional test cases. Additional test cases cover selects with i16/i8 conditions that are only 128/256-bits wide, but the compares are 512-bits wide and can only produce k-registers. We should be able to artificially widen the selects to avoid moving the k-register to an xmm/ymm register. llvm-svn: 322449
* X86: Add pattern matching for PMADDWDZvi Rackover2018-01-131-555/+127
| | | | | | | | | | | | | | | In addition to the existing match as part of a loop-reduction, add a straightforward pattern match for DAG-contained patterns. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D41811 llvm-svn: 322446
* [X86] Regenerate double shift testsSimon Pilgrim2018-01-133-47/+70
| | | | llvm-svn: 322444
* [InstSimplify] fold implied null ptr check (PR35790)Sanjay Patel2018-01-131-24/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This extends rL322327 to handle the pointer cast and should solve: https://bugs.llvm.org/show_bug.cgi?id=35790 Name: or_eq_zero %isnull = icmp eq i64* %p, null %x = ptrtoint i64* %p to i64 %somebits = and i64 %x, %y %somebits_are_zero = icmp eq i64 %somebits, 0 %or = or i1 %somebits_are_zero, %isnull => %or = %somebits_are_zero Name: and_ne_zero %isnotnull = icmp ne i64* %p, null %x = ptrtoint i64* %p to i64 %somebits = and i64 %x, %y %somebits_are_not_zero = icmp ne i64 %somebits, 0 %and = and i1 %somebits_are_not_zero, %isnotnull => %and = %somebits_are_not_zero https://rise4fun.com/Alive/CQ3 llvm-svn: 322439
* [X86][MMX] Add test for MMX zero foldingSimon Pilgrim2018-01-131-0/+113
| | | | | | As discussed in D41908 llvm-svn: 322436
* X86 Tests: add more pamddwd cases. NFCZvi Rackover2018-01-131-0/+482
| | | | | | Improve coverage of D41811 llvm-svn: 322434
* [X86] Add DAG combine to promote vXi1 result of a vXi8/vXi16 setcc when we ↵Craig Topper2018-01-132-100/+72
| | | | | | | | have AVX512 but not BWI. This avoids having the result type stick around until lowering where we have to extend the setcc and insert a truncate. If we get the types converted early we can do more to optimize it. llvm-svn: 322432
* XFAIL a test on Darwin, line-table stuck on DWARF 2Paul Robinson2018-01-131-0/+3
| | | | llvm-svn: 322430
* [hwasan] An LLVM flag to disable stack tag randomization.Evgeniy Stepanov2018-01-131-0/+7
| | | | | | | | | | | | Summary: Necessary to achieve consistent test results. Reviewers: kcc, alekseyshl Subscribers: kubamracek, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D42023 llvm-svn: 322429
* [MachineOutliner] Move hasAddressTaken check to MachineOutliner.cppJessica Paquette2018-01-131-0/+2
| | | | | | | | | | | | | *Mostly* NFC. Still updating the test though just for completeness. This moves the hasAddressTaken check to MachineOutliner.cpp and replaces it with a per-basic block test rather than a per-function test. The old test was too conservative and was preventing functions in C programs from being outlined even though they were safe to outline. This was mostly a problem in C sources. llvm-svn: 322425
* [AMDGPU] stop image_store being moved illegallyTim Renouf2018-01-122-20/+60
| | | | | | | | | | | | | | | | | | | | Summary: A recent change 321556: AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores can allow the machine instruction scheduler to move an image store past an image load using the same descriptor. V2: Fixed by marking image ops as mayAlias and isAliased. This may be overly conservative, and we may need to revisit. V3: Reverted test change done on 321556. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: llvm-commits, t-tye, yaxunl, wdng, kzhuravl Differential Revision: https://reviews.llvm.org/D41969 llvm-svn: 322419
* [InstSimplify] add tests for implied ptr cmp with null (PR35790); NFCSanjay Patel2018-01-121-2/+155
| | | | llvm-svn: 322411
* Allow unaligned access to ELF file data structures.Rui Ueyama2018-01-123-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ELF specification says that all ELF data structures are aligned to their natural alignments both in memory and file. That means when we access mmap'ed ELF files, we could assume that all data structures are aligned properly. However, in reality, we assume that the data structures are aligned only to two bytes because .a files only guarantee that their member files are aligned to two bytes in archive files. So the data access is already unaligned. This patch relaxes the alignment requirement even more, so that we accept unaligned access to all ELF data structures. This patch in particular makes lld bug-compatible with icc. Intel C compiler doesn't seem to care about data alignment and generates unaligned relocation sections (https://bugs.llvm.org/show_bug.cgi?id=35854). I also saw another instance of compatibility issues with our internal tool which creates unaligned section headers. Because GNU linkers are not picky about alignment, looks like it is not uncommon that ELF-generating tools create unaligned files. There is a performance penalty with this patch on host machines on which unaligned access is expensive. x86 and AArch64 are fine. ARMv6 is a problem, but I don't think using ARMv6 machines as hosts is common, so I believe it's not a real problem. Differential Revision: https://reviews.llvm.org/D41978 llvm-svn: 322407
* [NFC] Change MemIntrinsicInst::setAlignment() to take an unsigned instead of ↵Daniel Neilson2018-01-121-1/+1
| | | | | | | | | | | a Constant Summary: In preparation for https://reviews.llvm.org/D41675 this NFC changes this prototype of MemIntrinsicInst::setAlignment() to accept an unsigned instead of a Constant. llvm-svn: 322403
* AMDGPU/SI: Add d16 support for buffer intrinsics.Changpeng Fang2018-01-126-0/+332
| | | | | | | | | | Differential Revision: https://reviews.llvm.org/D38906 Reviewers: Matt and Brian. llvm-svn: 322402
* [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2018-01-124-0/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: See D37528 for a previous (non-deferred) version of this patch and its description. Preserves dominance in a deferred manner using a new class DeferredDominance. This reduces the performance impact of updating the DominatorTree at every edge insertion and deletion. A user may call DDT->flush() within JumpThreading for an up-to-date DT. This patch currently has one flush() at the end of runImpl() to ensure DT is preserved across the pass. LVI is also preserved to help subsequent passes such as CorrelatedValuePropagation. LVI is simpler to maintain and is done immediately (not deferred). The code to perform the preversation was minimally altered and simply marked as preserved for the PassManager to be informed. This extends the analysis available to JumpThreading for future enhancements such as threading across loop headers. Reviewers: dberlin, kuhar, sebpop Reviewed By: kuhar, sebpop Subscribers: mgorny, dmgreen, kuba, rnk, rsmith, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40146 llvm-svn: 322401
* Try to fix more bots after r322391Paul Robinson2018-01-121-1/+0
| | | | llvm-svn: 322400
* Add toothpicks to test from r322391Paul Robinson2018-01-121-2/+2
| | | | llvm-svn: 322394
* [DWARFv5] CodeGen support for MD5 file checksumsPaul Robinson2018-01-121-0/+49
| | | | | | | | | | Pass MD5 checksums through from IR to assembly/object files. After this, getting Clang to compute the MD5 should be the last step to supporting MD5 in the DWARF v5 line table header. Differential Revision: https://reviews.llvm.org/D41926 llvm-svn: 322391
* [X86][SSE] Force blend domains on stack folding testsSimon Pilgrim2018-01-122-7/+18
| | | | llvm-svn: 322385
* [X86][AVX] Regenerate element insertion testsSimon Pilgrim2018-01-121-2/+7
| | | | llvm-svn: 322384
* Allow dso_local on ifunc.Rafael Espindola2018-01-121-2/+2
| | | | | | | | | | | | | | | | | | | It was never fully disallowed. We were rejecting it in the asm parser, but not in the verifier. Currently TargetMachine::shouldAssumeDSOLocal returns true for hidden ifuncs. I considered changing it and moving the check from the asm parser to the verifier. The reason for deciding to allow it instead is that all linkers handle a direct reference just fine. They use the plt address as the address of the function. In fact doing that means that clang doesn't have the same bug as gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83782. This patch then removes the check from the asm parser and updates the bitcode reader and writer. llvm-svn: 322378
* [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate ↵Benjamin Kramer2018-01-121-0/+135
| | | | | | | | | the immediate I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. llvm-svn: 322373
* [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAPNemanja Ivanovic2018-01-122-0/+138
| | | | | | | | | | | | Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812. This patch ensures that the compare operand for the atomic compare and swap is properly zero-extended to 32 bits if applicable. A follow-up commit will fix the extension for the SETCC node generated when expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix. Differential Revision: https://reviews.llvm.org/D41856 llvm-svn: 322372
* Revert "[PowerPC] Manually schedule the prologue and epilogue"Stefan Pintilie2018-01-125-52/+50
| | | | | | | This reverts commit r322124 since some tests were broken by that patch. Will recommmit once the patch is fixed. llvm-svn: 322369
* [ARM GlobalISel] Add inst selector tests for G_FMADiana Picus2018-01-122-0/+253
| | | | | | | We don't yet match all the patterns involving G_FMA. Add tests for some of the ones that we do match. llvm-svn: 322368
* [ARM GlobalISel] Map G_FMA to FPRDiana Picus2018-01-121-2/+58
| | | | llvm-svn: 322367
* [ARM GlobalISel] Legalize G_FMADiana Picus2018-01-121-0/+121
| | | | | | | | | | | For hard float with VFP4, it is legal. Otherwise, we use libcalls. This needs a bit of support in the LegalizerHelper for soft float because we didn't handle G_FMA libcalls yet. The support is trivial, as the only difference between G_FMA and other libcalls that we already handle is that it has 3 input operands rather than just 2. llvm-svn: 322366
* [IRCE][NFC] Make range check's End a non-null SCEVMax Kazantsev2018-01-121-1/+1
| | | | | | | | | | | | | Currently, IRC contains `Begin` and `Step` as SCEVs and `End` as value. Aside from that, `End` can also be `nullptr` which can be later conditionally converted into a non-null SCEV. To make this logic more transparent, this patch makes `End` a SCEV and calculates it early, so that it is never a null. Differential Revision: https://reviews.llvm.org/D39590 llvm-svn: 322364
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