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* [GlobalISel][X86] Fix G_TRUNC instruction selection.Igor Breger2017-05-2126-89/+95
| | | | | | | | Updated tests with -verify-machineinstrs flag. It fixes 3 tests failed with machine verifier enabled and listed in PR27481 llvm-svn: 303502
* SummaryHiroshi Inoue2017-05-211-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC backend eliminates compare instructions by using record-form instructions in PPCInstrInfo::optimizeCompareInstr, which is called from peephole optimization pass. This patch improves this optimization to eliminate more compare instructions in two types of common case. - comparison against a constant 1 or -1 The record-form instructions set CR bit based on signed comparison against 0. So, the current implementation does not exploit the record-form instruction for comparison against a non-zero constant. This patch enables record-form optimization for constant of 1 or -1 if possible; it changes the condition "greater than -1" into "greater than or equal to 0" and "less than 1" into "less than or equal to 0". With this patch, compare can be eliminated in the following code sequence, as an example. uint64_t a, b; if ((a | b) & 0x8000000000000000ull) { ... } else { ... } - andi for 32-bit comparison on PPC64 Since record-form instructions execute 64-bit signed comparison and so we have limitation in eliminating 32-bit comparison, i.e. with cmplwi, using the record-form. The original implementation already has such checks but andi. is not recognized as an instruction which executes implicit zero extension and hence safe to convert into record-form if used for equality check. %1 = and i32 %a, 10 %2 = icmp ne i32 %1, 0 br i1 %2, label %foo, label %bar In this simple example, LLVM generates andi. + cmplwi + beq on PPC64. This patch make it possible to eliminate the cmplwi for this case. I added andi. for optimization targets if it is safe to do so. Differential Revision: https://reviews.llvm.org/D30081 llvm-svn: 303500
* Revert "[SCEV] Clarify behavior around max backedge taken count"Sanjoy Das2017-05-212-6/+6
| | | | | | | This reverts commit r303497 since it breaks the msan bootstrap bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1379/ llvm-svn: 303498
* [SCEV] Clarify behavior around max backedge taken countSanjoy Das2017-05-212-6/+6
| | | | | | | | | | | | | | | | | | | This change makes the split between the "exact" backedge taken count and the "maximum" backedge taken count a bit more obvious. Both of these are upper bounds on the number of times the loop header executes (since SCEV does not account for most kinds of abnormal control flow), but the latter is guaranteed to be a constant. There were a few places where the max backedge taken count *was* a non-constant; I've changed those to compute constants instead. At this point, I'm not sure if the constant max backedge count can be computed by calling `getUnsignedRange(Exact).getUnsignedMax()` without losing precision. If it can, we can simplify even further by making `getMaxBackedgeTakenCount` a thin wrapper around `getBackedgeTakenCount` and `getUnsignedRange`. llvm-svn: 303497
* Revert "Add pthread_self function prototype and make it speculatable."Xin Tong2017-05-211-38/+0
| | | | | | | | This reverts commit 143d7445b5dfa2f6d6c45bdbe0433d9fc531be21. Build breaking llvm-svn: 303496
* Add pthread_self function prototype and make it speculatable.Xin Tong2017-05-201-0/+38
| | | | | | | | | | | | | | Summary: This allows pthread_self to be pulled out of a loop by LICM. Reviewers: hfinkel, arsenm, davide Reviewed By: davide Subscribers: davide, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D32782 llvm-svn: 303495
* llvm-symbolizer: Support multiple CUs in a single DWO fileDavid Blaikie2017-05-203-0/+7
| | | | llvm-svn: 303482
* Add functionality to cvtres to parse all entries in res file.Eric Beckmann2017-05-205-0/+51
| | | | | | | | | | | Summary: Added the new modules in the Object/ folder. Updated the llvm-cvtres interface as well, and added additional tests. Subscribers: llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D33180 llvm-svn: 303480
* [NewGVN] Create a StoreExpression instead of a VariableExpression.Davide Italiano2017-05-201-0/+26
| | | | | | | | | | | | | In the case where we have an operand defined by a lod of the same memory location. Historically this was a VariableExpression because we wanted to make sure they ended up in the same class, but if we create the right expression, they end up in the same class anyway. Fixes PR32897. Thanks to Dan for the detailed discussion and the fix suggestion. llvm-svn: 303475
* Revert "Revert "ThinLTO: Verify bitcode before lauching the ↵Adrian Prantl2017-05-203-2/+62
| | | | | | | | | | | | | ThinLTOCodeGenerator."" This reapplies commit r303438 modified to not verify cross-imported bitcode in FunctionImporter. rdar://problem/31233625 Differential Revision: https://reviews.llvm.org/D33370 llvm-svn: 303470
* Revert "ThinLTO: Verify bitcode before lauching the ThinLTOCodeGenerator."Adrian Prantl2017-05-193-62/+2
| | | | | | This reverts commit r303438 while deliberating buildbot breakage. llvm-svn: 303467
* SimplifyLibCalls: Optimize wcslenMatthias Braun2017-05-194-0/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the strlen optimization code to work for both strlen and wcslen. This especially helps with programs in the wild where people pass L"string"s to const std::wstring& function parameters and the wstring constructor gets inlined. This also fixes a lingerind API problem/bug in getConstantStringInfo() where zeroinitializers would always give you an empty string (without a length) back regardless of the actual length of the initializer which did not work well in the TrimAtNul==false causing the PR mentioned below. Note that the fixed getConstantStringInfo() needed fixes to SelectionDAG memcpy lowering and may lead to some cases for out-of-bounds zeroinitializer accesses not getting optimized anymore. So some code with UB may produce out of bound memory reads now instead of just producing zeros. The refactoring "accidentally" fixes http://llvm.org/PR32124 Differential Revision: https://reviews.llvm.org/D32839 llvm-svn: 303461
* [safestack] Disable stack coloring by default.Evgeniy Stepanov2017-05-194-6/+6
| | | | | | Workaround for apparent miscompilation of PR32143. llvm-svn: 303456
* NewGVN: Fix PR32838.Daniel Berlin2017-05-191-0/+157
| | | | | | | | | | This is a complicated bug involving two issues: 1. What do we do with phi nodes when we prove all arguments are not live? 2. When is it safe to use value leaders to determine if we can ignore an argumnet? llvm-svn: 303453
* Fix line-endings.Simon Pilgrim2017-05-191-1/+1
| | | | llvm-svn: 303448
* [InstCombine] *Actually* commit the test showing the miscompile.Davide Italiano2017-05-191-1/+13
| | | | | | Clarify a comment while I'm here. llvm-svn: 303447
* Resubmit "[CodeView] Provide a common interface for type collections."Zachary Turner2017-05-191-2/+2
| | | | | | | | | | | | This was originally reverted because it was a breaking a bunch of bots and the breakage was not surfacing on Windows. After much head-scratching this was ultimately traced back to a bug in the lit test runner related to its pipe handling. Now that the bug in lit is fixed, Windows correctly reports these test failures, and as such I have finally (hopefully) fixed all of them in this patch. llvm-svn: 303446
* [InstCombine] Add tests to demonstrate the miscompile in PR33078.Davide Italiano2017-05-191-0/+39
| | | | llvm-svn: 303445
* Last of the major pieces to NewGVN - yay!Daniel Berlin2017-05-192-10/+425
| | | | | | | | | | | | | | | | | | | | | | Summary: NewGVN: Handle equivalence between phi of ops and op of phis. This makes our GVN mostly-complete. It would be complete, modulo some deliberate choices we make. This means it detects roughly all herband equivalences in polynomial time, including cases notoriously hard for other GVN's to detect. It also detects a very large swath of the cases we currently rely on instcombine to detect that involve folding upwards through phis. Fixes PR 31125, 31463, PR 31868 Reviewers: davide Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D32151 llvm-svn: 303444
* [DAGCombine] (addcarry 0, 0, X) -> (ext/trunc X)Amaury Sechet2017-05-195-2417/+2234
| | | | | | | | | | | | | | | Summary: While this makes some case better and some case worse - so it's unclear if it is a worthy combine just by itself - this is a useful canonicalisation. As per discussion in D32756 . Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32916 llvm-svn: 303441
* ThinLTO: Verify bitcode before lauching the ThinLTOCodeGenerator.Adrian Prantl2017-05-193-2/+62
| | | | | | | | rdar://problem/31233625 Differential Revision: https://reviews.llvm.org/D33151 llvm-svn: 303438
* Fix typo in testMatthias Braun2017-05-191-1/+1
| | | | llvm-svn: 303436
* [X86][FMA] Tests showing missed fmsubadd opportunities (PR30633)Simon Pilgrim2017-05-191-0/+193
| | | | llvm-svn: 303435
* [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literalsDmitry Preobrazhensky2017-05-191-0/+3
| | | | | | | | | | See bug 32922: https://bugs.llvm.org//show_bug.cgi?id=32922 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32912 llvm-svn: 303428
* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-192-0/+52
| | | | | | | | | | | | See Bugs 33019, 33056: https://bugs.llvm.org//show_bug.cgi?id=33019 https://bugs.llvm.org//show_bug.cgi?id=33056 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33288 llvm-svn: 303423
* [X86][AVX512] Make i1 illegal in the CodeGenGuy Blank2017-05-1931-761/+474
| | | | | | | | | | This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
* [GlobalISel] IRTranslator: Translate ConstantStructVolkan Keles2017-05-191-0/+30
| | | | | | | | | | | | Reviewers: qcolombet, ab, t.p.northover, aditya_nandakumar, dsanders Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33317 llvm-svn: 303412
* Revert "[CodeView] Provide a common interface for type collections."Zachary Turner2017-05-191-2/+2
| | | | | | | | | | | | | | | | | | This is a squash of ~5 reverts of, well, pretty much everything I did today. Something is seriously broken with lit on Windows right now, and as a result assertions that fire in tests are triggering failures. I've been breaking non-Windows bots all day which has seriously confused me because all my tests have been passing, and after running lit with -a to view the output even on successful runs, I find out that the tool is crashing and yet lit is still reporting it as a success! At this point I don't even know where to start, so rather than leave the tree broken for who knows how long, I will get this back to green, and then once lit is fixed on Windows, hopefully hopefully fix the remaining set of problems for real. llvm-svn: 303409
* [NewGVN] Delete the old store when we find congruent to a load.Davide Italiano2017-05-191-0/+59
| | | | | | | (or non-store, more in general). Fixes PR33086. Caught by the store verifier. llvm-svn: 303406
* Fix a broken test.Zachary Turner2017-05-191-2/+2
| | | | | | | | | | | | Similar to my previous fix, it turns out llvm-pdbdump has been printing an incorrect value since the beginning of time, but we didn't know it was incorrect. Specifically, we were interpreting a TypeIndex as referencing a type from the TPI stream when it actually should come from the IPI stream. So we were printing a string that looked like a valid string, but was just from the wrong place. llvm-svn: 303403
* LiveIntervalAnalysis: Fix missing case in pruneSubRegValues()Matthias Braun2017-05-191-0/+31
| | | | | | | | | | pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
* [NewGVN] Break infinite recursion in singleReachablePHIPath().Davide Italiano2017-05-181-0/+54
| | | | | | | | | | | | We can have cycles between PHIs and this causes singleReachablePhi() to call itself indefintely (until we run out of stack). The proper solution would be that of computing SCCs, but it's not worth for now, so just keep a visited set and give up when we find a cycle. Thanks to Dan for the discussion/help with this. Fixes PR33014. llvm-svn: 303393
* [llvm-pdbdump] Add the ability to merge PDBs.Zachary Turner2017-05-183-0/+128
| | | | | | | | | | | | | | | Merging PDBs is a feature that will be used heavily by the linker. The functionality already exists but does not have deep test coverage because it's not easily exposed through any tools. This patch aims to address that by adding the ability to merge PDBs via llvm-pdbdump. It takes arbitrarily many PDBs and outputs a single PDB. Using this new functionality, a test is added for merging type records. Future patches will add the ability to merge symbol records, module information, etc. llvm-svn: 303389
* [InstCombine] add more tests for xor-of-icmps; NFCSanjay Patel2017-05-181-0/+30
| | | | llvm-svn: 303387
* [NewGVN] Replace predicate info leftovers.Davide Italiano2017-05-181-0/+24
| | | | | | | This time with an additional fix, i.e. we remove the dead @llvm.ssa.copy instruction. llvm-svn: 303385
* [InstSimplify] Make m_Not work for xor -1, XCraig Topper2017-05-181-0/+8
| | | | | | | | Currently m_Not only works the canonical xor X, -1 form that InstCombine produces. InstSimplify can't rely on this canonicalization. Differential Revision: https://reviews.llvm.org/D33331 llvm-svn: 303379
* Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."Hans Wennborg2017-05-1850-1446/+1409
| | | | | | | | | This also reverts follow-ups r303292 and r303298. It broke some Chromium tests under MSan, and apparently also internal tests at Google. llvm-svn: 303369
* [InstSimplify] Add test cases for missing fold (A & B) | ~(A ^ B) -> ~(A ^ B).Craig Topper2017-05-181-0/+68
| | | | llvm-svn: 303367
* [InstCombine] move test and use better checks; NFCSanjay Patel2017-05-182-10/+17
| | | | | | Previously, this test was checking for 'or i1', but that was actually matched by 'xor i1'. llvm-svn: 303364
* [LSR] Call canonicalize after we generate a new Formula in ↵Wei Mi2017-05-181-0/+36
| | | | | | | | | | | | | | GenerateTruncates. Fix PR33077. The testcase in PR33077 generates a LSR Use Formula with two SCEVAddRecExprs for the same loop. Such uncommon formula will become non-canonical after GenerateTruncates adds sign extension to the ScaledReg of the Formula, and it will break the assertion that every Formula to be inserted is canonical. The fix is to call canonicalize for the raw Formula generated by GenerateTruncates before inserting it. llvm-svn: 303361
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-182-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* [JumpThreading] Dont RAUW condition incorrectlyAnna Thomas2017-05-183-2/+140
| | | | | | | | | | | | | | | | | | | Summary: We have a bug when RAUWing the condition if experimental.guard or assumes is a use of that condition. This is because LazyValueInfo may have used the guards/assumes to identify the value of the condition at the end of the block. RAUW replaces the uses at the guard/assume as well as uses before the guard/assume. Both of these are incorrect. For now, disable RAUW for conditions and fix the logic as a next step: https://reviews.llvm.org/D33257 Reviewers: sanjoy, reames, trentxintong Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33279 llvm-svn: 303349
* [AMDGPU] SDWA operands should not intersect with potential MIsSam Kolton2017-05-181-0/+50
| | | | | | | | | | | | | | | | | | | Summary: There should be no intesection between SDWA operands and potential MIs. E.g.: ``` v_and_b32 v0, 0xff, v1 -> src:v1 sel:BYTE_0 v_and_b32 v2, 0xff, v0 -> src:v0 sel:BYTE_0 v_add_u32 v3, v4, v2 ``` In that example it is possible that we would fold 2nd instruction into 3rd (v_add_u32_sdwa) and then try to fold 1st instruction into 2nd (that was already destroyed). So if SDWAOperand is also a potential MI then do not apply it. Reviewers: vpykhtin, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D32804 llvm-svn: 303347
* [MVT] add v1i1 MVTGuy Blank2017-05-181-1/+1
| | | | | | | | Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
* [GlobalISel][X86] G_ADD/G_SUB vector legalizer/selector support.Igor Breger2017-05-1816-0/+2125
| | | | | | | | | | | | | | Summary: G_ADD/G_SUB vector legalizer/selector support. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33232 llvm-svn: 303345
* [X86][AVX512] Add 512-bit vector ctpop costs + testsSimon Pilgrim2017-05-181-0/+63
| | | | llvm-svn: 303342
* Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-181-0/+35
| | | | | | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 The previous commit failed on test-suite/Bitcode/simd_ops/AArch64_halide_runtime.bc because isImmOperandEqual() assumed MO was a register operand and that's not always true. llvm-svn: 303341
* [X86] Add explicit triple to test invocationZvi Rackover2017-05-182-50/+50
| | | | llvm-svn: 303340
* [X86] Replace slow LEA instructions in X86Lama Saba2017-05-182-0/+1550
| | | | | | | | | | | | | | | According to Intel's Optimization Reference Manual for SNB+: " For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must dispatch via port 1: - LEA that has all three source operands: base, index, and offset - LEA that uses base and index registers where the base is EBP, RBP,or R13 - LEA that uses RIP relative addressing mode - LEA that uses 16-bit addressing mode " This patch currently handles the first 2 cases only. Differential Revision: https://reviews.llvm.org/D32277 llvm-svn: 303333
* Fix buildbot failure after rL303327: [BPI] Reduce the probability of ↵Serguei Katkov2017-05-181-1/+1
| | | | | | | | unreachable edge to minimal value greater than 0. One more test is updated to meet new branch probability for unreachable branches. llvm-svn: 303329
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