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* Merging r338716:Hans Wennborg2018-08-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338716 | spatel | 2018-08-02 15:46:20 +0200 (Thu, 02 Aug 2018) | 41 lines [ValueTracking] fix maxnum miscompile for cannotBeOrderedLessThanZero (PR37776) This adds the NAN checks suggested in PR37776: https://bugs.llvm.org/show_bug.cgi?id=37776 If both operands to maxnum are NAN, that should get constant folded, so we don't have to handle that case. This is the same assumption as other FP ops in this function. Returning 'false' is always conservatively correct. Copying from the bug report: Currently, we have this for "when is cannotBeOrderedLessThanZero (mustBePositiveOrNaN) true for maxnum": L ------------------- | Pos | Neg | NaN | ------------------------ |Pos | x | x | x | ------------------------ R |Neg | x | | x | ------------------------ |NaN | x | x | x | ------------------------ The cases with (Neg & NaN) are wrong. We should have: L ------------------- | Pos | Neg | NaN | ------------------------ |Pos | x | x | x | ------------------------ R |Neg | x | | | ------------------------ |NaN | x | | x | ------------------------ Differential Revision: https://reviews.llvm.org/D50081 ------------------------------------------------------------------------ llvm-svn: 339234
* Merging r338915:Hans Wennborg2018-08-071-0/+59
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r338915 | ctopper | 2018-08-03 22:14:18 +0200 (Fri, 03 Aug 2018) | 5 lines [SelectionDAG] Teach LegalizeVectorTypes to widen the mask input to a masked store. The mask operand is visited before the data operand so we need to be able to widen it. Fixes PR38436. ------------------------------------------------------------------------ llvm-svn: 339106
* Merging r338610:Hans Wennborg2018-08-072-18/+10
| | | | | | | | | | | | ------------------------------------------------------------------------ r338610 | jvesely | 2018-08-01 20:36:07 +0200 (Wed, 01 Aug 2018) | 3 lines AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS Non ext aligned i32 loads are still optimized to use CONSTANT_BUFFER (AS 8) ------------------------------------------------------------------------ llvm-svn: 339105
* Merging r338968:Hans Wennborg2018-08-071-12/+0
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338968 | echristo | 2018-08-05 16:23:37 +0200 (Sun, 05 Aug 2018) | 6 lines Revert "Add a warning if someone attempts to add extra section flags to sections" There are a bunch of edge cases and inconsistencies in how we're emitting sections cause this warning to fire and it needs more work. This reverts commit r335558. ------------------------------------------------------------------------ llvm-svn: 339099
* Merging r338665:Hans Wennborg2018-08-071-3/+22
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338665 | lliu0 | 2018-08-02 03:54:12 +0200 (Thu, 02 Aug 2018) | 11 lines Fix FCOPYSIGN expansion In expansion of FCOPYSIGN, the shift node is missing when the two operands of FCOPYSIGN are of the same size. We should always generate shift node (if the required shift bit is not zero) to put the sign bit into the right position, regardless of the size of underlying types. Differential Revision: https://reviews.llvm.org/D49973 ------------------------------------------------------------------------ llvm-svn: 339098
* Merging r338817:Hans Wennborg2018-08-072-36/+9
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338817 | inouehrs | 2018-08-03 07:39:48 +0200 (Fri, 03 Aug 2018) | 10 lines [InstSimplify] fold extracting from std::pair (2/2) This is the second patch of the series which intends to enable jump threading for an inlined method whose return type is std::pair<int, bool> or std::pair<bool, int>. The first patch is https://reviews.llvm.org/rL338485. This patch handles code sequences that merges two values using `shl` and `or`, then extracts one value using `and`. Differential Revision: https://reviews.llvm.org/D49981 ------------------------------------------------------------------------ llvm-svn: 339097
* Merging r338599:Hans Wennborg2018-08-031-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338599 | vlad.tsyrklevich | 2018-08-01 19:44:37 +0200 (Wed, 01 Aug 2018) | 16 lines [X86] FastISel fall back on !absolute_symbol GVs Summary: D25878, which added support for !absolute_symbol for normal X86 ISel, did not add support for materializing references to absolute symbols for X86 FastISel. This causes build failures because FastISel generates PC-relative relocations for absolute symbols. Fall back to normal ISel for references to !absolute_symbol GVs. Fix for PR38200. Reviewers: pcc, craig.topper Reviewed By: pcc Subscribers: hiraditya, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D50116 ------------------------------------------------------------------------ llvm-svn: 338847
* Merging r338703 and r338709:Hans Wennborg2018-08-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338703 | bd1976llvm | 2018-08-02 13:27:38 +0200 (Thu, 02 Aug 2018) | 8 lines [llvm-ar] Correct help text Corrected and simplified the help text. It was clearly too difficult to maintain before (see e.g. @227296) making it simpler and more consistent it should help people keep it up to date. Differential Revision: https://reviews.llvm.org/D48577 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r338709 | bd1976llvm | 2018-08-02 14:27:01 +0200 (Thu, 02 Aug 2018) | 3 lines [llvm-ar] Fix help text test. NFC. Missed from @338703 ------------------------------------------------------------------------ llvm-svn: 338840
* Merging r338554:Hans Wennborg2018-08-021-0/+30
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338554 | bryanpkc | 2018-08-01 15:50:29 +0200 (Wed, 01 Aug 2018) | 11 lines [AArch64] Fix FCCMP with FP16 operands Summary: This patch adds support for FCCMP instruction with FP16 operands, avoiding an assertion during instruction selection. Reviewers: olista01, SjoerdMeijer, t.p.northover, javed.absar Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D50115 ------------------------------------------------------------------------ llvm-svn: 338692
* Merging r338658:Hans Wennborg2018-08-021-204/+153
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338658 | nemanjai | 2018-08-02 02:03:22 +0200 (Thu, 02 Aug 2018) | 13 lines [PowerPC] Do not round values prior to converting to integer Adding the FP_ROUND nodes when combining FP_TO_[SU]INT of elements feeding a BUILD_VECTOR into an FP_TO_[SU]INT of the built vector loses precision. This patch removes the code that adds these nodes to true f64 operands. It also adds patterns required to ensure the code is still vectorized rather than converting individual elements and inserting into a vector. Fixes https://bugs.llvm.org/show_bug.cgi?id=38342 Differential Revision: https://reviews.llvm.org/D50121 ------------------------------------------------------------------------ llvm-svn: 338678
* [llvm-mca][x86] Add CMPS/LODS/MOVS/STOS string instruction resource testsSimon Pilgrim2018-08-0110-9/+529
| | | | llvm-svn: 338532
* [MC] Report fatal error for DWARF types for non-ELF object filesJonas Devlieghere2018-08-012-4/+10
| | | | | | | | | | | | | | Getting the DWARF types section is only implemented for ELF object files. We already disabled emitting debug types in clang (r337717), but now we also report an fatal error (rather than crashing) when trying to obtain this section in MC. Additionally we ignore the generate debug types flag for unsupported target triples. See PR38190 for more information. Differential revision: https://reviews.llvm.org/D50057 llvm-svn: 338527
* [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor2018-08-011-0/+113
| | | | | | | | | | | | | | | Summary: Add _L to _LZ image intrinsic table mapping to table gen. In ISelLowering check if image intrinsic has lod and if it's equal to zero, if so remove lod and change opcode to equivalent mapped _LZ. Change-Id: Ie24cd7e788e2195d846c7bd256151178cbb9ec71 Subscribers: arsenm, mehdi_amini, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D49483 llvm-svn: 338523
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
* [llvm-mca][x86] Add STC + STD instruction resource testsSimon Pilgrim2018-08-0110-10/+80
| | | | llvm-svn: 338514
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-015-0/+193
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* Revert "Enrich inline messages", tests failDavid Bolvansky2018-08-0112-50/+39
| | | | llvm-svn: 338496
* Enrich inline messagesDavid Bolvansky2018-08-0112-39/+50
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch improves Inliner to provide causes/reasons for negative inline decisions. 1. It adds one new message field to InlineCost to report causes for Always and Never instances. All Never and Always instantiations must provide a simple message. 2. Several functions that used to return the inlining results as boolean are changed to return InlineResult which carries the cause for negative decision. 3. Changed remark priniting and debug output messages to provide the additional messages and related inline cost. 4. Adjusted tests for changed printing. Patch by: yrouban (Yevgeny Rouban) Reviewers: craig.topper, sammccall, sgraenitz, NutshellySima, shchenz, chandlerc, apilipenko, javed.absar, tejohnson, dblaikie, sanjoy, eraman, xbolva00 Reviewed By: tejohnson, xbolva00 Subscribers: xbolva00, llvm-commits, arsenm, mehdi_amini, eraman, haicheng, steven_wu, dexonsmith Differential Revision: https://reviews.llvm.org/D49412 llvm-svn: 338494
* [AArch64] Disallow the MachO specific .loh directive for windowsMartin Storsjo2018-08-011-0/+4
| | | | | | | | Also add a test for it being unsupported for linux. Differential Revision: https://reviews.llvm.org/D49929 llvm-svn: 338493
* [DWARF] Basic support for producing DWARFv5 .debug_addr sectionVictor Leschuk2018-08-011-0/+79
| | | | | | | | | | | | | | This revision implements support for generating DWARFv5 .debug_addr section. The implementation is pretty straight-forward: we just check the dwarf version and emit section header if needed. Reviewers: aprantl, dblaikie, probinson Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D50005 llvm-svn: 338487
* [InstSimplify] fold extracting from std::pair (1/2)Hiroshi Inoue2018-08-011-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to enable jump threading when a method whose return type is std::pair<int, bool> or std::pair<bool, int> is inlined. For example, jump threading does not happen for the if statement in func. std::pair<int, bool> callee(int v) { int a = dummy(v); if (a) return std::make_pair(dummy(v), true); else return std::make_pair(v, v < 0); } int func(int v) { std::pair<int, bool> rc = callee(v); if (rc.second) { // do something } SROA executed before the method inlining replaces std::pair by i64 without splitting in both callee and func since at this point no access to the individual fields is seen to SROA. After inlining, jump threading fails to identify that the incoming value is a constant due to additional instructions (like or, and, trunc). This series of patch add patterns in InstructionSimplify to fold extraction of members of std::pair. To help jump threading, actually we need to optimize the code sequence spanning multiple BBs. These patches does not handle phi by itself, but these additional patterns help NewGVN pass, which calls instsimplify to check opportunities for simplifying instructions over phi, apply phi-of-ops optimization to result in successful jump threading. SimplifyDemandedBits in InstCombine, can do more general optimization but this patch aims to provide opportunities for other optimizers by supporting a simple but common case in InstSimplify. This first patch in the series handles code sequences that merges two values using shl and or and then extracts one value using lshr. Differential Revision: https://reviews.llvm.org/D48828 llvm-svn: 338485
* [X86] Adding more test patterns for lea-opt (PR37939)Jatin Bhateja2018-08-011-0/+151
| | | | | | | | Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50128 llvm-svn: 338483
* [x86] Fix a really subtle miscompile due to a somewhat glaring bug inChandler Carruth2018-08-011-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy lowering. If you have a branch of LLVM, you may want to cherrypick this. It is extremely unlikely to hit this case empirically, but it will likely manifest as an "impossible" branch being taken somewhere, and will be ... very hard to debug. Hitting this requires complex conditions living across complex control flow combined with some interesting memory (non-stack) initialized with the results of a comparison. Also, because you have to arrange for an EFLAGS copy to be in *just* the right place, almost anything you do to the code will hide the bug. I was unable to reduce anything remotely resembling a "good" test case from the place where I hit it, and so instead I have constructed synthetic MIR testing that directly exercises the bug in question (as well as the good behavior for completeness). The issue is that we would mistakenly assume any SETcc with a valid condition and an initial operand that was a register and a virtual register at that to be a register *defining* SETcc... It isn't though.... This would in turn cause us to test some other bizarre register, typically the base pointer of some memory. Now, testing this register and using that to branch on doesn't make any sense. It even fails the machine verifier (if you are running it) due to the wrong register class. But it will make it through LLVM, assemble, and it *looks* fine... But wow do you get a very unsual and surprising branch taken in your actual code. The fix is to actually check what kind of SETcc instruction we're dealing with. Because there are a bunch of them, I just test the may-store bit in the instruction. I've also added an assert for sanity that ensure we are, in fact, *defining* the register operand. =D llvm-svn: 338481
* [x86/slh] Add unwind info to several tests to make it more obvious thatChandler Carruth2018-08-011-12/+48
| | | | | | | | | | | we aren't incorrectly generating any of it when doing SLH. There was a bug that only occured with SLH that very much looked like it could be caused by bad unwind info, and so this was a prime suspect. Turns out that everything is fine, but this way we'll *see* if we end up, for example, putting things we shouldn't inside the prolog. llvm-svn: 338480
* [DebugInfo] Generate fixups as emitting DWARF .debug_line.Hsiangkai Wang2018-08-012-0/+77
| | | | | | | | | | | | | | | | It is necessary to generate fixups in .debug_line as relaxation is enabled due to the address delta may be changed after relaxation. DWARF will record the mappings of lines and addresses in .debug_line section. It will encode the information using special opcodes, standard opcodes and extended opcodes in Line Number Program. I use DW_LNS_fixed_advance_pc to encode fixed length address delta and DW_LNE_set_address to encode absolute address to make it possible to generate fixups in .debug_line section. Differential Revision: https://reviews.llvm.org/D46850 llvm-svn: 338477
* [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate.Amara Emerson2018-08-013-5/+24
| | | | | | | | | | | | Previously we were just visiting the blocks in the function in IR order, which is rather arbitrary. Therefore we wouldn't always visit defs before uses, but the translation code relies on this assumption in some places. Only codegen change seen in tests is an elision of a redundant copy. Fixes PR38396 llvm-svn: 338476
* AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov2018-08-017-35/+155
| | | | | | Differential Revision: https://reviews.llvm.org/D49874 llvm-svn: 338470
* [PATCH] [SLC] Test simplification of pow() for vector types (NFC)Evandro Menezes2018-08-011-0/+95
| | | | | | | Add test case for the simplification of `pow()` for vector types that D50035 enables. llvm-svn: 338463
* Revert r338354 "[ARM] Revert r337821"Reid Kleckner2018-07-313-11/+11
| | | | | | | | | | | | | | | | | Disable ARMCodeGenPrepare by default again. It is causing verifier failues in V8 that look like: Duplicate integer as switch case switch i32 %trunc, label %if.end13 [ i32 0, label %cleanup36 i32 0, label %if.then8 ], !dbg !4981 i32 0 fatal error: error in backend: Broken function found, compilation aborted! I will continue reducing the test case and send it along. llvm-svn: 338452
* [WebAssembly] Fix debug info tests after r338437.David L. Jones2018-07-311-19/+13
| | | | | | | After r338437, debug_ranges are no longer emitted. Previously, this was only done for DWARF version 5 and above. llvm-svn: 338448
* [DWARF] Support for .debug_addr (consumer)Victor Leschuk2018-07-3115-0/+343
| | | | | | | This patch implements basic support for parsing and dumping DWARFv5 .debug_addr section. llvm-svn: 338447
* [llvm-objcopy] Make --strip-debug strip .gdb_indexFangrui Song2018-07-311-1/+7
| | | | | | | | | | | | | | | | | Summary: See binutils-gdb/bfd/elf.c, GNU objcopy also strips .stab* (STABS) .line* (DWARF 1) .gnu.linkonce.wi.* (linkonce section for .debug_info) but I'm not sure we need to be compatible with it. Reviewers: dblaikie, alexshap, jakehehrlich, jhenderson Reviewed By: alexshap, jakehehrlich Subscribers: aprantl, JDevlieghere, jakehehrlich, llvm-commits Differential Revision: https://reviews.llvm.org/D50100 llvm-svn: 338443
* Revert r338431: "Add DebugCounters to DivRemPairs"George Burgess IV2018-07-311-90/+0
| | | | | | | This reverts r338431; the test it added is making buildbots unhappy. Locally, I can repro the failure on reverse-iteration builds. llvm-svn: 338442
* AMDGPU: Split amdgcn/r600 fminnum/fmaxnum testsMatt Arsenault2018-07-314-443/+667
| | | | | | | R600 breaks on too many things to usefully test changes with ieee_mode on vs. off. llvm-svn: 338435
* Add DebugCounters to DivRemPairsGeorge Burgess IV2018-07-311-0/+90
| | | | | | | | | | For people who don't use DebugCounters, NFCI. Patch by Zhizhou Yang! Differential Revision: https://reviews.llvm.org/D50033 llvm-svn: 338431
* [CodeView] Add coverage test for r338308 (Fixed crash in type merging)Alexandre Ganea2018-07-311-0/+15
| | | | llvm-svn: 338423
* AMDGPU: Break 64-bit arguments into 32-bit piecesMatt Arsenault2018-07-311-7/+43
| | | | llvm-svn: 338421
* AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on callsMatt Arsenault2018-07-313-13/+71
| | | | | | | This improves code for the same reasons as scalarizing 32-bit element vectors. llvm-svn: 338418
* [CodeView] Minimal support for S_UNAMESPACE recordsAlexandre Ganea2018-07-311-0/+51
| | | | | | Differential Revision: https://reviews.llvm.org/D50007 llvm-svn: 338417
* AMDGPU: Scalarize vector argument types to callsMatt Arsenault2018-07-313-32/+71
| | | | | | | | | | | | | | | | | When lowering calling conventions, prefer to decompose vectors into the constitute register types. This avoids artifical constraints to satisfy a wide super-register. This improves code quality because now optimizations don't need to deal with the super-register constraint. For example the immediate folding code doesn't deal with 4 component reg_sequences, so by breaking the register down earlier the existing immediate folding code is able to work. This also avoids the need for the shader input processing code to manually split vector types. llvm-svn: 338416
* Revert "[DebugInfo] Generate DWARF debug information for labels."Vlad Tsyrklevich2018-07-312-134/+0
| | | | | | | This reverts commits r338390 and r338398, they were causing LSan failures on the ASan bot. llvm-svn: 338408
* [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)Simon Pilgrim2018-07-314-504/+235
| | | | | | | | | | As was done for vector rotations, we can efficiently use ISD::MULHU for vXi8/vXi16 ISD::SRL lowering. Shift-by-zero cases are still problematic (mainly on v32i8 due to extra AND/ANDN/OR or VPBLENDVB blend masks but v8i16/v16i16 aren't great either if PBLENDW fails) so I've limited this first patch to known non-zero cases if we can't easily use PBLENDW. Differential Revision: https://reviews.llvm.org/D49562 llvm-svn: 338407
* [llvm-mca][x86] Add 32-bit instruction resource testsSimon Pilgrim2018-07-3110-0/+792
| | | | | | These aren't exhaustive, but cover some instructions that are only available in 32-bit mode (where would we be without good BCD math performance?). llvm-svn: 338404
* Resubmit r338340 "[MS Demangler] Better demangling of template arguments."Zachary Turner2018-07-311-0/+53
| | | | | | This broke the build with GCC, but has since been fixed. llvm-svn: 338403
* [X86] Add pattern matching for PMADDUBSWCraig Topper2018-07-311-1788/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Similar to D49636, but for PMADDUBSW. This instruction has the additional complexity that the addition of the two products saturates to 16-bits rather than wrapping around. And one operand is treated as signed and the other as unsigned. A C example that triggers this pattern ``` static const int N = 128; int8_t A[2*N]; uint8_t B[2*N]; int16_t C[N]; void foo() { for (int i = 0; i != N; ++i) C[i] = MIN(MAX((int16_t)A[2*i]*(int16_t)B[2*i] + (int16_t)A[2*i+1]*(int16_t)B[2*i+1], -32768), 32767); } ``` Reviewers: RKSimon, spatel, zvi Reviewed By: RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D49829 llvm-svn: 338402
* [X86] Add test cases that could use PMADDUBSW.Craig Topper2018-07-311-0/+2233
| | | | llvm-svn: 338401
* [X86] Preserve more liveness information in emitStackProbeInlineFrancis Visoiu Mistrih2018-07-312-7/+24
| | | | | | | | | | | | | | | | This commit fixes two issues with the liveness information after the call: 1) The code always spills RCX and RDX if InProlog == true, which results in an use of undefined phys reg. 2) FinalReg, JoinReg, RoundedReg, SizeReg are not added as live-ins to the basic blocks that use them, therefore they are seen undefined. https://llvm.org/PR38376 Differential Revision: https://reviews.llvm.org/D50020 llvm-svn: 338400
* [DebugInfo] Fix build failed in 'clang-cmake-armv8-full'.Hsiangkai Wang2018-07-311-8/+16
| | | | | | | | Builder clang-cmake-armv8-full failed due to the assembly 'comment' notation is not '#' in the target. So, I use CHECK-SAME to avoid to check the comment notation in the same line in the test case. llvm-svn: 338398
* Fix InstCombine address space assertEwan Crawford2018-07-311-0/+19
| | | | | | | | | | | | | | | | | | | | | Workaround bug where the InstCombine pass was asserting on the IR added in lit test, where we have a bitcast instruction after a GEP from an addrspace cast. The second bitcast in the test was getting combined into `bitcast <16 x i32>* %0 to <16 x i32> addrspace(3)*`, which looks like it should be an addrspace cast instruction instead. Otherwise if control flow is allowed to continue as it is now we create a GEP instruction `<badref> = getelementptr inbounds <16 x i32>, <16 x i32>* %0, i32 0`. However because the type of this instruction doesn't match the address space we hit an assert when replacing the bitcast with that GEP. ``` void llvm::Value::doRAUW(llvm::Value*, bool): Assertion `New->getType() == getType() && "replaceAllUses of value with new value of different type!"' failed. ``` Differential Revision: https://reviews.llvm.org/D50058 llvm-svn: 338395
* [InstCombine] regenerate checks and add tests for D50035; NFCSanjay Patel2018-07-311-234/+367
| | | | llvm-svn: 338392
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