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* Reverted r333424 as it broke multiple build bots and left unfixed for a long ↵Galina Kistanova2018-05-301-36/+3
| | | | | | time llvm-svn: 333578
* [dsymutil] Escape HTML special characters in plist.Jonas Devlieghere2018-05-301-2/+2
| | | | | | | | | | When printing string in the Plist, we weren't escaping the characters which lead to invalid XML. This patch adds the escape logic to StringExtras. rdar://39785334 llvm-svn: 333565
* [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in ↵Alexander Ivchenko2018-05-291-3/+36
| | | | | | | | | | | | | | .note.gnu.property This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property sections. These notes indicate that the object file is built to support Intel CET. patch by mike.dvoretsky Differential Revision: https://reviews.llvm.org/D47473 llvm-svn: 333424
* [X86][Sched] Add InstRW for CLC on Intel after SNB.Clement Courbet2018-05-299-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After SNB, Intel CPUs can rename CF independently of other EFLAGS, so the renamer can zero it for free. Note that STC still consumes resources. To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC` On SNB: ``` --- key: opcode_name: CLC mode: uops config: '' cpu_name: sandybridge llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: '3', value: 0.0014, debug_string: SBPort0 } - { key: '4', value: 0.0013, debug_string: SBPort1 } - { key: '5', value: 0.0003, debug_string: SBPort4 } - { key: '6', value: 0.0029, debug_string: SBPort5 } - { key: '10', value: 0.0003, debug_string: SBPort23 } error: '' info: 'instruction is serial, repeating a random one. Snippet: CLC ' ... ``` On HSW: ``` --- key: opcode_name: CLC mode: uops config: '' cpu_name: haswell llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: '3', value: 0.001, debug_string: HWPort0 } - { key: '4', value: 0.0009, debug_string: HWPort1 } - { key: '5', value: 0.0004, debug_string: HWPort2 } - { key: '6', value: 0.0006, debug_string: HWPort3 } - { key: '7', value: 0.0002, debug_string: HWPort4 } - { key: '8', value: 0.0012, debug_string: HWPort5 } - { key: '9', value: 0.0022, debug_string: HWPort6 } - { key: '10', value: 0.0001, debug_string: HWPort7 } error: '' info: 'instruction is serial, repeating a random one. Snippet: CLC ' ... ``` Reviewers: craig.topper, RKSimon Subscribers: gchatelet, llvm-commits Differential Revision: https://reviews.llvm.org/D47362 llvm-svn: 333392
* [dwarfdump] Make -c and -p work togetherJonas Devlieghere2018-05-261-0/+309
| | | | | | | | | | | | | When requesting to dump both the parent chain and children, we used to print the DIE more than once because we propagated the dump options to the parent without clearing the respective flags. This commit fixes this oversight and adds a test. rdar://39415292 Differential revision: https://reviews.llvm.org/D47263 llvm-svn: 333350
* [llvm-objcopy] Add --keep-file-symbols optionPaul Semel2018-05-261-0/+70
| | | | | | | | This option prevent from removing file symbols while removing symbols. Differential Revision: https://reviews.llvm.org/D46830 llvm-svn: 333339
* [X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)Simon Pilgrim2018-05-251-5/+5
| | | | | | | | As confirmed by llvm-exegesis, there is no scheduler difference between MOVDQA/MOVDQU and VMOVDQA/VMOVDQU xmm reg-reg moves Another chapter in the never ending crusade to remove useless InstRW overrides from the x86 scheduler models...... llvm-svn: 333271
* [llvm-objcopy] Add --strip-unneeded optionPaul Semel2018-05-251-0/+136
| | | | | | Differential Revision: https://reviews.llvm.org/D46896 llvm-svn: 333267
* [UpdateTestChecks] Improved update_mca_test_checks block analysisGreg Bedwell2018-05-2424-816/+726
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously update_mca_test_checks worked entirely at "block" level where a block is some sequence of lines delimited by at least one empty line. This generally worked well, but could sometimes lead to excessive repetition of check lines for various prefixes if some block was almost identical between prefixes, but not quite (for example, due to a different dispatch width in the otherwise identical summary views). This new analyis attempts to split blocks further in the case where the following conditions are met: a) There is some prefix common to every RUN line (typically 'ALL'). b) The first line of the block is common to the output with every prefix. c) The block has the same number of lines for the output with every prefix. Also, regenerated all llvm-mca test files with the following command: update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s" The new analysis showed a "multiple lines not disambiguated by prefixes" warning for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some explicit prefixes to each of the RUN lines in that test. Differential Revision: https://reviews.llvm.org/D47321 llvm-svn: 333204
* [Support] Add color cl category.Jonas Devlieghere2018-05-242-0/+4
| | | | | | | | | This commit adds a color category so tools can document this option and enables it for dwarfdump and dsymuttil. rdar://problem/40498996 llvm-svn: 333176
* [llvm-strip] Minor fix of the usage of TableGenAlexander Shaposhnikov2018-05-231-0/+4
| | | | | | | | | | | | This is a small follow-up to the revisions r333117 and r331663. 1. Avoid the name conflicts of the generated variables for prefixes. 2. Apply clang-format -i -style=llvm to llvm-objcopy.cpp once again. 3. Add a test for the flag with double dash. Test plan: make check-all llvm-svn: 333120
* [llvm-strip] Expose --keep-symbol optionAlexander Shaposhnikov2018-05-231-0/+8
| | | | | | | | | | Expose --keep-symbol option in llvm-strip. Test plan: make check-all Differential revision: https://reviews.llvm.org/D47222 llvm-svn: 333117
* [llvm-mca] Print the "Block RThroughput" in the SummaryView.Andrea Di Biagio2018-05-2320-100/+120
| | | | | | | | | | | | | | | | | | | This patch implements the "block reciprocal throughput" computation in the SummaryView. The block reciprocal throughput is computed as the MAX of: - NumMicroOps / DispatchWidth - Resource Cycles / #Units (for every resource consumed). The block throughput is bounded from above by the hardware dispatch throughput. That is because the DispatchWidth is an upper bound on how many opcodes can be part of a single dispatch group. The block throughput is also limited by the amount of hardware parallelism. The number of available resource units affects how the resource pressure is distributed, and also how many blocks can be delivered every cycle. llvm-svn: 333095
* [llvm-objcopy] Fix the behavior of --strip-* and --keep-symbolAlexander Shaposhnikov2018-05-221-0/+57
| | | | | | | | | | | | If one runs llvm-objcopy --strip-all --keep-symbol foo and the symbol table indeed contains the symbol "foo" then it should not be removed. Test plan: make check-all Differential revision: https://reviews.llvm.org/D47052 llvm-svn: 333008
* Revert "[llvm-objcopy] Add --strip-unneeded option"Paul Semel2018-05-221-136/+0
| | | | | | | | There is a use after free I didn't see. Need to investigate. This reverts commit f7624abeb1f0d012309baf2e78cf2499fbfe5e5f. llvm-svn: 332925
* [llvm-objcopy] Add --strip-unneeded optionPaul Semel2018-05-211-0/+136
| | | | | | | | This option removes symbols that are not needed by relocations. Differential Revision: https://reviews.llvm.org/D46896 llvm-svn: 332915
* LTO: Replace split dwarf implementation that uses objcopy with one that uses ↵Peter Collingbourne2018-05-211-8/+6
| | | | | | | | | | direct emission. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47091 llvm-svn: 332884
* [DebugInfo] Use absolute addresses in location listsJonas Devlieghere2018-05-212-6/+6
| | | | | | | | | | | Rather than relying on the user to do the address calculating in DW_AT_location we should just dump the absolute address. rdar://problem/38513870 Differential revision: https://reviews.llvm.org/D47152 llvm-svn: 332873
* [llvm-mca] Removed an empty line generated by the timeline view. NFC.Andrea Di Biagio2018-05-2127-165/+637
| | | | | | Also, regenerate all tests. llvm-svn: 332853
* [X86][BtVer2] Add a 'J' prefix to the PRF/RCU defs. NFCAndrea Di Biagio2018-05-219-18/+18
| | | | | | | This is to keep the Jaguar model's naming convention. Processor resources all have a 'J' prefix in the BtVer2 scheduling model. llvm-svn: 332851
* win: try to fix dia tests with newer msvc versionsNico Weber2018-05-211-1/+1
| | | | llvm-svn: 332827
* [X86] Add GPR<->XMM Schedule TagsSimon Pilgrim2018-05-185-41/+41
| | | | | | | | | | BtVer2 - fix NumMicroOp and account for the Lat+6cy GPR->XMM and Lat+1cy XMm->GPR delays (see rL332737) The high number of MOVD/MOVQ equivalent instructions meant that there were a number of missed patterns in SNB/Znver1: SNB - add missing GPR<->MMX costs (taken from Agner / Intel AOM) Znver1 - add missing GPR<->XMM MOVQ costs (taken from Agner) llvm-svn: 332745
* [X86][BtVer2] Improve simulation of (V)PINSR valuesSimon Pilgrim2018-05-183-16/+16
| | | | | | Include the 6cy delay transferring from the GPR to FPU. llvm-svn: 332737
* [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latencySimon Pilgrim2018-05-184-18/+18
| | | | llvm-svn: 332722
* [X86][SSE] Ensure vector partial load/stores use the ↵Simon Pilgrim2018-05-185-18/+18
| | | | | | | | | | WriteVecLoad/WriteVecStore scheduler classes Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc. Fixes BtVer2/SLM which have different behaviours for GPR stores. llvm-svn: 332718
* [X86][SSE] Ensure float load/stores use the WriteFLoad/WriteFStore scheduler ↵Simon Pilgrim2018-05-185-27/+27
| | | | | | | | | | classes Retag some instructions that were missed when we split off vector load/store/moves - MOVSS/MOVSD/MOVHPD/MOVHPD/MOVLPD/MOVLPS etc. Fixes BtVer2/SLM which have different behaviours for GPR stores. llvm-svn: 332714
* [llvm-mca][X86] Add CMOV test filesSimon Pilgrim2018-05-179-0/+2928
| | | | llvm-svn: 332622
* [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUBSimon Pilgrim2018-05-171-91/+91
| | | | llvm-svn: 332616
* [llvm-mca] add flag -all-views and flag -all-stats.Andrea Di Biagio2018-05-174-0/+442
| | | | | | | Flag -all-views enables all the views. Flag -all-stats enables all the views that print hardware statistics. llvm-svn: 332602
* [llvm-mca][X86] Add ADX test filesSimon Pilgrim2018-05-174-0/+234
| | | | llvm-svn: 332595
* [X86] Fix typo in instregex for CVTSI642SDrrSimon Pilgrim2018-05-162-4/+4
| | | | llvm-svn: 332510
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-16157-42121/+42121
| | | | llvm-svn: 332447
* [llvm-objcopy] Add --only-keep-debug as a noopJake Ehrlich2018-05-151-0/+20
| | | | | | | | | | | | | | | | | | | This option just keeps being a problem and really needs to be implemented in some fashion. Implementing it properly requires some kind of "replaceSectionReference" method because all the existing links need to be maintained. The desired behavior is just for allocated sections to become NOBITS but actually implementing that is rather tricky due to the current design of llvm-objcopy. However converting allocated sections to NOBITS is just an optimization and not something debuggers need. Debuggers can debug a stripped executable and take an unstripped executable for that stripped executable as input. Additionally allocated sections account for a very small part of debug binaries so this optimization is quite small. I propose that for the time being we implement this as a NOP so that people can use llvm-objcopy where they need to, just in a sub-optimal way. This option has already blocked a lot of people and its currently blocking me. llvm-svn: 332396
* [llvm-rc] Add support for the optional CLASS statement for dialogsMartin Storsjo2018-05-152-0/+32
| | | | | | Differential Revision: https://reviews.llvm.org/D46875 llvm-svn: 332386
* [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim2018-05-152-9/+9
| | | | | | | | BtVer2 - Fixes schedules for (V)CVTPS2PD instructions A lot of the Intel models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first llvm-svn: 332376
* [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classesSimon Pilgrim2018-05-152-4/+4
| | | | | | | | | Btver2 - VCVTPH2PSYrm needs to double pump the AGU Broadwell - missing VCVTPS2PH*mr stores extra latency Allows us to remove the WriteCvtF2FSt conversion store class llvm-svn: 332357
* [llvm-objcopy] Add --keep-symbol (-K) optionPaul Semel2018-05-152-0/+102
| | | | | | | | | This option permits to explicitly keep the specified symbol so that it doesn't get removed. Differential Revision: https://reviews.llvm.org/D46819 llvm-svn: 332356
* Reapply "DWARFVerifier: Check "completeness" of .debug_names section"Pavel Labath2018-05-151-0/+195
| | | | | | | | | This is a resubmit of r331868 (D46583), which was reverted due to failures on the PS4 bot. These have been resolved with r332246/D46748. llvm-svn: 332349
* [llvm-mca][x86] Add F16C instruction testsSimon Pilgrim2018-05-155-0/+302
| | | | llvm-svn: 332347
* [llvm-rc] Add support for parsing memory flagsMartin Storsjo2018-05-154-0/+401
| | | | | | | | | | | | | | | | | | | | | | | | Most of the handling is pretty straightforward; fetch the default memory flags for the specific resource type before parsing the flags and apply them on top of that, except that some flags imply others and some flags clear more than one flag. For icons and cursors, the flags set get passed on to all individual single icon/cursor resources, while only some flags affect the icon/cursor group resource. For stringtables, the behaviour is pretty simple; the first stringtable resource of a bundle sets the flags for the whole bundle. The output of these tests match rc.exe byte for byte. The actual use of these memory flags is deprecated and they have no effect since Win16, but some resource script files may still happen to have them in place. Differential Revision: https://reviews.llvm.org/D46818 llvm-svn: 332329
* [llvm-rc] Read the Planes/BitCount fields from BITMAPINFOHEADER for iconsMartin Storsjo2018-05-151-1/+1
| | | | | | | | | | | | | | | | Previously these fields were only read from this header for cursors, while Planes was hardcoded to 1 for icons (with a comment that it was unknown why this was needed) and BitCount was left at the value read originally in the RESDIRENTRY. This fixes the single byte that was differing for the icon/cursor test compared to rc.exe. This is based on research/testing by Nico Weber. Differential Revision: https://reviews.llvm.org/D46816 llvm-svn: 332328
* [llvm-rc] Add missing inputs for tag-icon-cursor.test.Martin Storsjo2018-05-147-28/+2
| | | | | | | | | | | | | | This adds the missing input files used for this test, except for the separate input files for specific error cases; matching test input files were provided by Nico Weber. The extra copying of files into the %t directory doesn't seem to be necessary since that directory only ever is used for output here, not for inputs. Differential Revision: https://reviews.llvm.org/D46813 llvm-svn: 332297
* [llvm-mca][X86] Add missing SSE4A test fileSimon Pilgrim2018-05-141-0/+55
| | | | llvm-svn: 332270
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-142-2/+2
| | | | | | MMX was missing and YMM was tagged as a fp nt store llvm-svn: 332269
* [llvm-mca][x86] Add scalar nt-store instruction testsSimon Pilgrim2018-05-149-9/+72
| | | | llvm-svn: 332262
* [llvm-mca][x86] Add and/not/or/xor instruction testsSimon Pilgrim2018-05-149-9/+2772
| | | | llvm-svn: 332257
* [X86][BtVer2] Model ymm move as double pumped instructionsSimon Pilgrim2018-05-111-13/+13
| | | | | | We still need to handle mmx/xmm moves as 'decode-only' no-pipe instructions llvm-svn: 332109
* [X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classesSimon Pilgrim2018-05-114-9/+9
| | | | | | Fixes an issue on SLM/Btver2 where we had instructions were being treated as scalar loads/stores llvm-svn: 332104
* [X86][SLM] Vector stores only use the MEC port.Simon Pilgrim2018-05-112-12/+12
| | | | | | | | Confirmed by both Agner and Intel's AOM - the IEC/FPC are not required for pure load/stores (even if its a partial update). Can't fix WriteStore until all RMW instructions are cleaned up though.... llvm-svn: 332096
* [X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector widthSimon Pilgrim2018-05-111-2/+2
| | | | | | Fixes a SNB issue that was missing vlddqu/vmovntdqa ymm instructions llvm-svn: 332094
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