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* [llvm-mca][x86] Add MOVBE resource tests to all supporting targetsSimon Pilgrim2018-07-179-0/+462
| | | | | | SNB doesn't support MOVBE but the numbers in Generic (which use the SNB model) look sane. llvm-svn: 337305
* [llvm-mca][x86] Add BSWAP resource testsSimon Pilgrim2018-07-1710-10/+80
| | | | llvm-svn: 337302
* [llvm-mca][x86] Add displacement-only and additional scale=1 LEA testsSimon Pilgrim2018-07-171-1/+82
| | | | llvm-svn: 337298
* [llvm-mca][x86] Add LEA resource tests (PR32326)Simon Pilgrim2018-07-171-0/+362
| | | | | | Add llvm-mca tests demonstrating how LEA instructions are currently modelled. Once this is working on btver2 I'll copy the test file to the other target directories. llvm-svn: 337297
* [llvm-objcopy] Run not with any python, but the python configured in lit.Benjamin Kramer2018-07-174-4/+4
| | | | llvm-svn: 337262
* [llvm-objcopy] Add support for large indexesJake Ehrlich2018-07-166-0/+80
| | | | | | | | | | | | | | | | | | | This patch is an update of an older patch that never landed (see here: https://reviews.llvm.org/D42516) Recently various users have run into this issue and it just 100% has to be solved at this point. The main difference in this patch is that I use gunzip instead of unzip which should hopefully allow tests to pass. Please review this as if it is a new patch however. I found some issues along the way and made some minor modifications. The binary used in this patch for testing (a zip file to make it small) can be found here: https://drive.google.com/file/d/1UjsnTO9edLttZibbr-2T1bJl92KEQFAO/view?usp=sharing Differential Revision: https://reviews.llvm.org/D49206 llvm-svn: 337204
* [cfi-verify] Abort on unsupported targetsJoel Galenson2018-07-162-0/+234
| | | | | | | | As suggested in the review for r337007, this makes cfi-verify abort on unsupported targets instead of producing incorrect results. It also updates the design document to reflect this. Differential Revision: https://reviews.llvm.org/D49304 llvm-svn: 337181
* [llvm-mca] Regenerate X86 specific tests. NFCAndrea Di Biagio2018-07-1513-15/+15
| | | | | | Not all tests were correctly updated by the update script after r336797. llvm-svn: 337124
* [llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio2018-07-155-62/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers. The goal of this patch is to improve the throughput analysis in llvm-mca for the case where instructions perform partial register writes. On x86, partial register writes are quite difficult to model, mainly because different processors tend to implement different register merging schemes in hardware. When the code contains partial register writes, the IPC (instructions per cycles) estimated by llvm-mca tends to diverge quite significantly from the observed IPC (using perf). Modern AMD processors (at least, from Bulldozer onwards) don't rename partial registers. Quoting Agner Fog's microarchitecture.pdf: " The processor always keeps the different parts of an integer register together. For example, AL and AH are not treated as independent by the out-of-order execution mechanism. An instruction that writes to part of a register will therefore have a false dependence on any previous write to the same register or any part of it." This patch is a first important step towards improving the analysis of partial register updates. It changes the semantic of RegisterFile descriptors in tablegen, and teaches llvm-mca how to identify false dependences in the presence of partial register writes (for more details: see the new code comments in include/Target/TargetSchedule.h - class RegisterFile). This patch doesn't address the case where a write to a part of a register is followed by a read from the whole register. On Intel chips, high8 registers (AH/BH/CH/DH)) can be stored in separate physical registers. However, a later (dirty) read of the full register (example: AX/EAX) triggers a merge uOp, which adds extra latency (and potentially affects the pipe usage). This is a very interesting article on the subject with a very informative answer from Peter Cordes: https://stackoverflow.com/questions/45660139/how-exactly-do-partial-registers-on-haswell-skylake-perform-writing-al-seems-to In future, the definition of RegisterFile can be extended with extra information that may be used to identify delays caused by merge opcodes triggered by a dirty read of a partial write. Differential Revision: https://reviews.llvm.org/D49196 llvm-svn: 337123
* Attempt to get test/tools/llvm-lib/help.test passing on ↵Nico Weber2018-07-141-1/+4
| | | | | | | | | | | sanitizer-x86_64-linux-fast The bot has a /b directory, so /? matches against that and gets expanded to it. (Thanks to Hans's r187366, which solved the same problem for clang-cl a while ago and which saved me much head scratching.) llvm-svn: 337092
* Give llvm-lib rudimentary help output.Nico Weber2018-07-141-0/+3
| | | | | | https://reviews.llvm.org/D49318 llvm-svn: 337084
* [dwarfdump] Add pretty printer for accelerator table based on Atom.Jonas Devlieghere2018-07-131-1/+1
| | | | | | | | For instance, When dumping .apple_types, the second atom represents the DW_TAG. In addition to printing the raw value, we now also pretty print the value if the ATOM tells us how. llvm-svn: 337026
* [llvm-mca][BtVer2] Add tests for dependency breaking instructions.Andrea Di Biagio2018-07-136-1/+412
| | | | llvm-svn: 337024
* [cfi-verify] Only run AArch64 tests when it is a supported targetJoel Galenson2018-07-131-0/+2
| | | | | | This stops the tests I added in r337007 from running when AArch64 is not a supported target. llvm-svn: 337012
* [cfi-verify] Support AArch64.Joel Galenson2018-07-132-0/+352
| | | | | | | | | | | | This patch adds support for AArch64 to cfi-verify. This required three changes to cfi-verify. First, it generalizes checking if an instruction is a trap by adding a new isTrap flag to TableGen (and defining it for x86 and AArch64). Second, the code that ensures that the operand register is not clobbered between the CFI check and the indirect call needs to allow a single dereference (in x86 this happens as part of the jump instruction). Third, we needed to ensure that return instructions are not counted as indirect branches. Technically, returns are indirect branches and can be covered by CFI, but LLVM's forward-edge CFI does not protect them, and x86 does not consider them, so we keep that behavior. In addition, we had to improve AArch64's code to evaluate the branch target of a MCInst to handle calls where the destination is not the first operand (which it often is not). Differential Revision: https://reviews.llvm.org/D48836 llvm-svn: 337007
* [XRay][compiler-rt] Add PID field to llvm-xray tool and add PID metadata ↵Dean Michael Berris2018-07-138-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | record entry in FDR mode Summary: llvm-xray changes: - account-mode - process-id {...} shows after thread-id - convert-mode - process {...} shows after thread - parses FDR and basic mode pid entries - Checks version number for FDR log parsing. Basic logging changes: - Update header version from 2 -> 3 FDR logging changes: - Update header version from 2 -> 3 - in writeBufferPreamble, there is an additional PID Metadata record (after thread id record and tsc record) Test cases changes: - fdr-mode.cc, fdr-single-thread.cc, fdr-thread-order.cc modified to catch process id output in the log. Reviewers: dberris Reviewed By: dberris Subscribers: hiraditya, llvm-commits, #sanitizers Differential Revision: https://reviews.llvm.org/D49153 llvm-svn: 336974
* [gold-plugin] Disable section ordering for relocatable linksBill Wendling2018-07-121-1/+1
| | | | | | | | | | | | Not all programs want section ordering when compiled with LTO. In particular, the Linux kernel is very sensitive when it comes to linking, and doesn't boot when each function is placed in its own sections. Reviewed By: pcc Differential Revision: https://reviews.llvm.org/D48756 llvm-svn: 336943
* Add --strip-all option back to llvm-strip.Stephen Hines2018-07-121-0/+8
| | | | | | | | | | | | | | | | | Summary: This option appears to have been dropped as part of the refactoring in r331663. Unfortunately, if we want to use llvm-strip as a drop-in replacement for strip, this option should still be available. Reviewers: alexshap Reviewed By: alexshap Subscribers: meikeb, kongyi, chh, jakehehrlich, llvm-commits, pirama Differential Revision: https://reviews.llvm.org/D49226 llvm-svn: 336921
* Revert "[llvm-objdump] Add -demangle (-C) option"Paul Semel2018-07-111-47/+0
| | | | | | | This reverts commit 3a44ccd156e0edd2e89226f8ed63928e227900bb. This reverts commit d5cfc836bb5552e20507d3612d13ff66ff9e36a0. llvm-svn: 336829
* Fix llvm-objdump demangle test (added triple option)Paul Semel2018-07-111-5/+5
| | | | llvm-svn: 336821
* [X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions.Andrea Di Biagio2018-07-1118-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Before revision 336728, the "mayLoad" flag for instruction (V)MOVLPSrm was inferred directly from the "default" pattern associated with the instruction definition. r336728 removed special node X86Movlps, and all the patterns associated to it. Now instruction (V)MOVLPSrm doesn't have a pattern associated to it, and the 'mayLoad/hasSideEffects' flags are left unset. When the instruction info is emitted by tablegen, method CodeGenDAGPatterns::InferInstructionFlags() sees that (V)MOVLPSrm doesn't have a pattern, and flags are undefined. So, it conservatively sets the "hasSideEffects" flag for it. As a consequence, we were losing the 'mayLoad' flag, and we were gaining a 'hasSideEffect' flag in its place. This patch fixes the issue (originally reported by Michael Holmen). The mca tests show the differences in the instruction info flags. Instructions that were affected by this problem were: MOVLPSrm/VMOVLPSrm/VMOVLPSZ128rm. Differential Revision: https://reviews.llvm.org/D49182 llvm-svn: 336818
* [llvm-objdump] Add -demangle (-C) optionPaul Semel2018-07-111-0/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D49043 llvm-svn: 336816
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-11212-2025/+2025
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [llvm-readobj] Add -hex-dump (-x) optionPaul Semel2018-07-111-0/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D48281 llvm-svn: 336782
* [llvm-mca] Add tests for partial register writes.Andrea Di Biagio2018-07-114-0/+310
| | | | | | | | | | llvm-mca doesn't know that on modern AMD processors, portions of a general purpose register are not treated independently. So, a partial register write has a false dependency on the super-register. The issue with partial register writes will be addressed by a follow-up patch. llvm-svn: 336778
* [dsymutil] Add support for outputting assemblyJonas Devlieghere2018-07-091-0/+3
| | | | | | | | | | | | | When implementing the DWARF accelerator tables in dsymutil I ran into an assertion in the assembler. Debugging these kind of issues is a lot easier when looking at the assembly instead of debugging the assembler itself. Since it's only a matter of creating an AsmStreamer instead of a MCObjectStreamer it made sense to turn this into a (hidden) dsymutil feature. Differential revision: https://reviews.llvm.org/D49079 llvm-svn: 336561
* [llvm-mca] report an error if the assembly sequence contains an unsupported ↵Andrea Di Biagio2018-07-091-0/+6
| | | | | | | | | | | | | instruction. This is a short-term fix for PR38093. For now, we llvm::report_fatal_error if the instruction builder finds an unsupported instruction in the instruction stream. We need to revisit this fix once we start addressing PR38101. Essentially, we need a better framework for error handling. llvm-svn: 336543
* [MCA][X86][NFC] Add BSF/BSR resource testsRoman Lebedev2018-07-0810-10/+400
| | | | | | | | | | | | Reviewers: RKSimon, andreadb, courbet Reviewed By: RKSimon Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48997 llvm-svn: 336510
* [llvm-objcopy] Add support for static librariesAlexander Shaposhnikov2018-07-064-1/+169
| | | | | | | | | | | This diff adds support for handling static libraries to llvm-objcopy and llvm-strip. Test plan: make check-all Differential revision: https://reviews.llvm.org/D48413 llvm-svn: 336455
* [llvm-mca] improve the instruction issue logic implemented by the Scheduler.Andrea Di Biagio2018-07-063-60/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the Scheduler heuristic used to select the next instruction to issue to the pipelines. The motivating example is test X86/BtVer2/add-sequence.s, for which llvm-mca wrongly reported an estimated IPC of 1.50. According to perf, the actual IPC for that test should have been ~2.00. It turns out that an IPC of 2.00 for test add-sequence.s cannot possibly be predicted by a Scheduler that only prioritizes instructions based on their "age". A similar issue also affected test X86/BtVer2/dependent-pmuld-paddd.s, for which llvm-mca wrongly estimated an IPC of 0.84 instead of an IPC of 1.00. Instructions in the ReadyQueue are now ranked based on two factors: - The "age" of an instruction. - The number of unique users of writes associated with an instruction. The new logic still prioritizes older instructions over younger instructions to minimize the pressure on the reorder buffer. However, the number of users of an instruction now also affects the overall rank. This potentially increases the ability of the Scheduler to extract instruction level parallelism. This patch fixes the problem with the wrong IPC reported for test add-sequence.s and test dependent-pmuld-paddd.s. llvm-svn: 336420
* Reapply: "objdump: Support newer ObjC image info flags"Dave Lee2018-07-061-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for two additional ObjC image info flags: `IS_SIMULATED` and `HAS_CATEGORY_CLASS_PROPERTIES`. `IS_SIMULATED` indicates a Mach-O binary built for iOS simulator. `HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler that supports class properties in categories. Reviewers: enderby, compnerd Reviewed By: compnerd Subscribers: keith, llvm-commits Differential Revision: https://reviews.llvm.org/D48568 llvm-svn: 336411
* Revert "objdump: Support newer ObjC image info flags"Dave Lee2018-07-061-7/+0
| | | | | | This reverts commit 8c4cc472e7a67bd3b2b20cc4cf32d31af29bc7e9. llvm-svn: 336402
* objdump: Support newer ObjC image info flagsDave Lee2018-07-051-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for two additional ObjC image info flags: `IS_SIMULATED` and `HAS_CATEGORY_CLASS_PROPERTIES`. `IS_SIMULATED` indicates a Mach-O binary built for iOS simulator. `HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler that supports class properties in categories. Reviewers: enderby, compnerd Reviewed By: compnerd Subscribers: keith, llvm-commits Differential Revision: https://reviews.llvm.org/D48568 llvm-svn: 336399
* [llvm-objdump] Removed archive-headers-disas testPaul Semel2018-07-051-29/+0
| | | | | | | | This test is failing because of the disas part. For the moment, I will juste remove it. I will add it again tomorrow with a proper fix. llvm-svn: 336370
* [llvm-objcopy] Fix timezone dependant testsPaul Semel2018-07-052-18/+18
| | | | llvm-svn: 336363
* [llvm-objdump] Add --archive-headers (-a) optionPaul Semel2018-07-053-0/+50
| | | | llvm-svn: 336357
* [X86][BtVer2][MCA][NFC] Add CMPEQ dependency-breaking one-idioms testsRoman Lebedev2018-07-042-0/+157
| | | | | | | | | | | | | | | | | | | Summary: As per `Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions)`, these, like zero-idioms, are dependency-breaking, although they produce ones and still consume resources. FIXME: as discussed in D48877, llvm-mca handling is broken for these. Reviewers: andreadb Reviewed By: andreadb Subscribers: gbedwell, RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D48876 llvm-svn: 336292
* [llvm-objdump] Add --file-headers (-f) optionPaul Semel2018-07-044-0/+63
| | | | llvm-svn: 336284
* NFC - Various typo fixes in testsGabor Buella2018-07-041-5/+5
| | | | llvm-svn: 336268
* Remove absolute path in testTeresa Johnson2018-07-021-1/+1
| | | | | | | My test change in r336148 accidentally included an absolute path, clean that up to fix bot failures. llvm-svn: 336151
* [ThinLTO] Fix printing of module paths for distributed backend indexesTeresa Johnson2018-07-021-0/+10
| | | | | | | | | | | | | | | | Summary: In the individual index files emitted for distributed ThinLTO backends, the module path ids are not contiguous. Assign slots to module paths in order to handle this better and also to get contiguous numbering in the summary assembly. Reviewers: davidxl, dexonsmith Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, steven_wu Differential Revision: https://reviews.llvm.org/D48698 llvm-svn: 336148
* Replace unused output filenames with /dev/null in testsFangrui Song2018-07-027-7/+7
| | | | | | Similar to rLLD336129 llvm-svn: 336131
* nm: Add -no-weak flag for hiding weak symbolsDave Lee2018-07-021-0/+1
| | | | | | | | | | | | | | | | | | Summary: This adds a new -no-weak flag to nm to hide weak symbols in its output. This also adds a -W alias for this which is analogous to -U. Patch by Keith Smiley Reviewers: kastiglione, enderby, compnerd Reviewed By: kastiglione Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48751 llvm-svn: 336126
* Revert "[llvm-readobj] Fix printing format"Paul Semel2018-07-011-8/+0
| | | | | | | There is a problem with the formatting on windows build. I need to investigate on this. llvm-svn: 336061
* [llvm-readobj] Fix printing formatPaul Semel2018-07-011-0/+8
| | | | | | | | | | | | We were printing every character, even those that weren't printable. It doesn't really make sense for this option. The string content was sticked to its address, added two spaces in between. Differential Revision: https://reviews.llvm.org/D48271 llvm-svn: 336058
* [dsymutil] Make the CachedBinaryHolder the defaultJonas Devlieghere2018-06-291-6/+6
| | | | | | | | Replaces all uses of the old binary holder with its cached variant. Differential revision: https://reviews.llvm.org/D48770 llvm-svn: 335991
* Require x86 for this test.Sterling Augustine2018-06-281-0/+1
| | | | llvm-svn: 335939
* [llvm-readobj] Add experimental support for SHT_RELR sectionsJake Ehrlich2018-06-283-0/+182
| | | | | | | | | | | | | | | This change adds experimental support for SHT_RELR sections, proposed here: https://groups.google.com/forum/#!topic/generic-abi/bX460iggiKg Definitions for the new ELF section type and dynamic array tags, as well as the encoding used in the new section are all under discussion and are subject to change. Use with caution! Author: rahulchaudhry Differential Revision: https://reviews.llvm.org/D47919 llvm-svn: 335922
* Some targets don't have lld built, so just use a binary copySterling Augustine2018-06-282-3/+1
| | | | | | of the input file. llvm-svn: 335908
* Handle absolute symbols as branch targets in disassembly.Sterling Augustine2018-06-281-0/+4
| | | | | | https://reviews.llvm.org/D48554 llvm-svn: 335903
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