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* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-069-30/+30
| | | | | | | Also, update a few tests to minimize the diff in D45369. No functional change intended. llvm-svn: 329403
* DWARFVerifier: validate information in name index entriesPavel Labath2018-04-062-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch add checks to verify that the information in the name index entries is consistent with the debug_info section. Specifically, we check that entries point to valid DIEs, and their names, tags, and compile units match the information in the debug_info sections. These checks are only run if the previous checks did not find any errors in the name index headers. Attempting to proceed with the checks anyway would likely produce a lot of spurious errors and the verification code would need to be very careful to avoid crashing. I also add a couple of more checks to the abbreviation-validation code to verify that some attributes are always present (an index without a DW_IDX_die_offset attribute is fairly useless). The entry verification works only on indexes without any type units - I haven't attempted to extend it to type units, as we don't even have a DWARF v5-compatible type unit generator at the moment. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45323 llvm-svn: 329392
* [debug_loc] Fix typo in DWARFExpression constructorPavel Labath2018-04-061-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The positions of the DwarfVersion and AddressSize arguments were reversed, which caused parsing for dwarf opcodes which contained address-size-dependent operands (such as DW_OP_addr). Amusingly enough, none of the address-size asserts fired, as dwarf version was always 4, which is a valid address size. I ran into this when constructing weird inputs for the DWARF verifier. I I add a test case as hand-written dwarf -- I am not sure how to trigger this differently, as having a DW_OP_addr inside a location list is a fairly non-standard thing to do. Fixing this error exposed a bug in the debug_loc.dwo parser, which was always being constructed with an address size of 0. I fix that as well by following the pattern in the non-dwo parser of picking up the address size from the first compile unit (which is technically not correct, but probably good enough in practice). Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45324 llvm-svn: 329381
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-49/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [gold] Add debug-pass-manager option, and use it to test new-pass-managerTeresa Johnson2018-04-051-0/+19
| | | | | | | | | | | | Summary: Follow up from r314963. Reviewers: pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45293 llvm-svn: 329249
* [X86][Btver2] Strip unnecessary check prefixes from resources testsSimon Pilgrim2018-04-0411-11/+11
| | | | llvm-svn: 329192
* [llvm-mca] Move the logic that prints register file statistics to its own ↵Andrea Di Biagio2018-04-035-5/+5
| | | | | | | | | | | | | view. NFCI Before this patch, the "BackendStatistics" view was responsible for printing the register file usage (as well as many other statistics). Now users can enable register file usage statistics using the command line flag `-register-file-stats`. By default, the tool doesn't print register file statistics. llvm-svn: 329083
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-035-13/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* Another attempt to fix papertrail-warnings.test on Windows bots by making ↵Douglas Yung2018-04-021-3/+3
| | | | | | expected message less case sensitive. llvm-svn: 329008
* [llvm-pdbutil] Add an export subcommand.Zachary Turner2018-04-022-0/+2
| | | | | | | | | | | | | | | | | This command can dump the binary contents of a stream to a file. This is useful when you want to do side-by-side comparisons of a specific stream from two PDBs to examine the differences between them. You can export both of them to a file, then open them up side by side in a hex editor (for example), so as to eliminate any differences that might arise from the contents being on different blocks in the PDB. In subsequent patches I plan to improve the "explain" subcommand so that you can explain the contents of a binary file that isn't necessarily a full PDB, but one of these dumped streams, by telling the subcommand how to interpret the contents. llvm-svn: 329002
* [llvm-mca] Do not assume that implicit reads cannot be associated with ↵Andrea Di Biagio2018-04-021-0/+26
| | | | | | | | | | ReadAdvance entries. Before, the instruction builder incorrectly assumed that only explicit reads could have been associated with ReadAdvance entries. This patch fixes the issue and adds a test to verify it. llvm-svn: 328972
* Attempt to fix papertrail-warnings.test on Windows bots.Nico Weber2018-04-021-2/+2
| | | | llvm-svn: 328971
* [dsymutil] Upstream emitting of papertrail warnings.Jonas Devlieghere2018-04-023-1/+32
| | | | | | | | | | When running dsymutil as part of your build system, it can be desirable for warnings to be part of the end product, rather than just being emitted to the output stream. This patch upstreams that functionality. Differential revision: https://reviews.llvm.org/D44639 llvm-svn: 328965
* [X86] Add SchedRW for PMULLDCraig Topper2018-03-313-29/+28
| | | | | | | | | | | | | | | | | | | Summary: It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput. This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet. I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs. Reviewers: RKSimon, GGanesh, courbet Reviewed By: RKSimon Subscribers: gchatelet, gbedwell, andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D44972 llvm-svn: 328914
* [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts andAndrea Di Biagio2018-03-301-8/+8
| | | | | | | | | VSQRT instructions. There were still a few AVX instructions with an incorrect number of opcodes. These should be fixed now. llvm-svn: 328892
* [X86][BtVer2] Fix the number of uOps for horizontal operations.Andrea Di Biagio2018-03-302-12/+12
| | | | llvm-svn: 328886
* [llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.Zachary Turner2018-03-302-0/+253
| | | | | | | | | This will show more detail when using `llvm-pdbutil explain` on an offset in the DBI or PDB streams. Specifically, it will dig into individual header fields and substreams to give a more precise description of what the byte represents. llvm-svn: 328878
* [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds andAndrea Di Biagio2018-03-303-12/+10
| | | | | | | | | most vector logic instructions. Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input operand. llvm-svn: 328867
* [X86][BtVer2] Add tests that show how ReadAfterLd is missing for someAndrea Di Biagio2018-03-304-0/+92
| | | | | | | | | | | | | instructions. In the Btver2 model, there are a few InstRW overrides that don't specify a ReadAfterLd for the register input operand. As a result, a few AVX variants of horizontal operations and most vector logic operations with a folded memory operand don't have a ReadAdvance info associated to their input register operands. llvm-svn: 328865
* [X86] Add llvm-mca tests for r328834.Andrea Di Biagio2018-03-304-0/+120
| | | | | | | | | Verify that the ReadAfterLd is correctly applied to FMA and 4-ops variable blend instructions. As Craig pointed out in D44726, some Intel models still have to be fixed. llvm-svn: 328861
* [X86] Add tests to verify the presence of "ReadAfterLd" after r328823.Andrea Di Biagio2018-03-302-0/+53
| | | | | | | This change adds a couple of tests to verify the change introduced by revision 328823 ([X86] Correct the placement of ReadAfterLd in BEXTR and BZHI). llvm-svn: 328859
* For llvm-nm and Mach-O files that are fully stripped, special case a ↵Kevin Enderby2018-03-292-0/+6
| | | | | | | | | | | | | | redacted LC_MAIN As a further refinement on: r328274 - For llvm-nm and Mach-O files also use function starts info in some cases when printing symbols we want to special case a redacted LC_MAIN so it is easier to find. rdar://38978929 llvm-svn: 328820
* [PDB] Print some more details when explaining MSF fields.Zachary Turner2018-03-291-0/+3
| | | | | | | | | | | When we determine that a field belongs to an MSF super block or the free page map, we wouldn't print any additional information. With this patch, we now print the value of the field (for super block fields) or the allocation status of the specified byte (in the case of offsets in the FPM). llvm-svn: 328808
* [PDB] Fix a bug in the explain subcommand.Zachary Turner2018-03-291-4/+4
| | | | | | | | We were trying to dig into the super block fields and print a description of the field at the specified offset, but we were printing the wrong field due to an off-by-one-field-error. llvm-svn: 328804
* [PDB] Add an explain subcommand.Zachary Turner2018-03-291-0/+83
| | | | | | | | | | | | | | | | | | | When investigating various things, we often have a file offset and what to know what's in the PDB at that address. For example we may be doing a binary comparison of two LLD-generated PDBs to look for sources of non-determinism, or we may wish to compare an LLD-generated PDB with a Microsoft generated PDB for sources of byte-for-byte incompatibility. In these cases, we can do a binary diff of the two files, and once we find a mismatched byte we can use explain to figure out what that byte is, immediately honining in on the problem. This patch implements this by trying to narrow the meaning of a particular file offset down as much as possible. Differential Revision: https://reviews.llvm.org/D44959 llvm-svn: 328799
* .debug_names: Correctly align the AugmentationStringSize fieldPavel Labath2018-03-291-0/+101
| | | | | | | | | | | | | We should align the value of the field, not the overall section offset. This distinction matters if one of the debug_names contributions is not of size which is a multiple of four. The dwarf producers may choose to emit rounded contributions, but they are not required to do so. In the latter case, without this patch we would corrupt the parsing state, as we would adjust the offset even if subsequent contributions contained correctly rounded augmentation strings. llvm-svn: 328796
* [llvm-mca] Correctly set the ReadAdvance information for register use operands.Andrea Di Biagio2018-03-291-0/+46
| | | | | | | | | | | | The tool was passing the wrong operand index to method MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and not the operand index. This was found when testing X86 code where instructions had a memory folded operand. This patch fixes the issue and adds test read-advance-1.s to ensure that the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used. llvm-svn: 328790
* .debug_names: Parse DW_IDX_die_offset as a referencePavel Labath2018-03-296-8/+8
| | | | | | | | | | | Before this patch we were parsing the attributes as section offsets, as that is what apple_names is doing. However, this is not correct as DWARF v5 specifies that this attribute should use the Reference form class. This also updates all the testcases (except the ones that deliberately pass a different form) to use the correct form class. llvm-svn: 328773
* [llvm-ar] Support multiple dashed optionsPeter Collingbourne2018-03-281-0/+16
| | | | | | | | | | | | | | | This allows syntax like: $ llvm-ar -c -r -u file.a file.o This is in addition to the other formats that are already supported: $ llvm-ar cru file.a file.o $ llvm-ar -cru file.a file.o Patch by Tom Anderson! Differential Revision: https://reviews.llvm.org/D44452 llvm-svn: 328716
* [X86][BtVer2] Fix the number of micro opcodes for AES[ENC|DEC] and other YMM ↵Andrea Di Biagio2018-03-281-22/+22
| | | | | | | | | | | instructions. Similar to r328694. The number of micro opcodes should be 2 for those instructions. This was found when testing AVX code for BtVer2 using llvm-mca. llvm-svn: 328698
* [X86][BtVer2] Fix the number of micro opcodes for a bunch of YMM instructions.Andrea Di Biagio2018-03-282-14/+709
| | | | | | | | | | | | | The Jaguar backend natively supports 128-bit data types. Operations on YMM registers are split into two COPs (complex operations). Each COP consumes a slot in the dispatch group, and in the reorder buffer. The scheduling model for Jaguar should mark those instructions as `let NumMicroOps = 2`. This was found when testing AVX code for BtVer2 using llvm-mca. llvm-svn: 328694
* [DWARF][DWARF v5]: Adding support for dumping DW_RLE_offset_pair and ↵Wolfgang Pieb2018-03-271-7/+37
| | | | | | | | | | DW_RLE_base_address Reviewers: dblakie, aprantl Differential Revision: https://reviews.llvm.org/D44811 llvm-svn: 328662
* [AArch64] Decorate AArch64 instrs with OPERAND_PCRELRafael Auler2018-03-271-0/+3
| | | | | | | | | | | | | | Summary: This is a canonical way to teach objdump to print the target symbols for branches when disassembling AArch64 code. Reviewers: evandro, t.p.northover, espindola Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D44851 llvm-svn: 328638
* [llvm-mca] pass the correct set of used registers in checkRAT.Andrea Di Biagio2018-03-271-0/+33
| | | | | | | | | We were incorrectly initializing the array of used registers in method checkRAT. As a consequence, the number of register file stalls was misreported. Added a test to cover this case. llvm-svn: 328629
* Revert "Revert "[lit] Generalized /dev/null support on Windows.""Mircea Trofin2018-03-271-1/+1
| | | | | | | | | | | | | | | | | Summary: This reverts commit r328596. Checking if the arguments are strings before testing if they contain "/dev/null". Reviewers: rnk Reviewed By: rnk Subscribers: delcypher, llvm-commits Differential Revision: https://reviews.llvm.org/D44914 llvm-svn: 328603
* Revert "[lit] Generalized /dev/null support on Windows."Mircea Trofin2018-03-261-1/+1
| | | | | | This reverts commit ca7fdbb974384ce5a05528b22a41d46b1cc13e92. llvm-svn: 328596
* [lit] Generalized /dev/null support on Windows.Mircea Trofin2018-03-261-1/+1
| | | | | | | | | | | | | | Generalized /dev/null remapping on Windows, and added test. Reviewers: rnk Reviewed By: rnk Subscribers: amccarth, zturner, delcypher, llvm-commits Differential Revision: https://reviews.llvm.org/D44771 llvm-svn: 328589
* [X86][Btver2] Add (U)COMISD/(U)COMISD scheduler costsSimon Pilgrim2018-03-263-16/+16
| | | | | | Account for the "+i" integer pipe transfer cost (1cy use of JALU0 for GPR PRF write) llvm-svn: 328573
* [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costsSimon Pilgrim2018-03-261-4/+4
| | | | | | We still need to account for how Jaguar passes data from GPR -> XMM, which isn't as clean as XMM -> GPR..... llvm-svn: 328551
* [X86][Btver2] Add CVTSD2SS/CVTSS2SD scheduler costsSimon Pilgrim2018-03-262-8/+8
| | | | llvm-svn: 328541
* [X86][Btver2] Account for the "+i" integer pipe transfer costs (1cy use of ↵Simon Pilgrim2018-03-265-30/+30
| | | | | | JALU0 for GPR PRF write) llvm-svn: 328536
* [X86][Btver2] Add CVTSD2SI/CVTSS2SI scheduler costsSimon Pilgrim2018-03-263-36/+45
| | | | | | | | Account for the "+i" integer pipe transfer cost (1cy use of JALU0 for GPR PRF write) This also adds missing vcvttss2si tests llvm-svn: 328505
* [X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP instructions costsSimon Pilgrim2018-03-261-12/+12
| | | | | | These should match the YMM MOVDUP/ PERMILPD/PERMILPS + SHUFPD/SHUFPS shuffles instead of using the WriteFShuffle defaults. llvm-svn: 328501
* [llvm-mca] Fix how views are added to the InstructionTables.Andrea Di Biagio2018-03-261-0/+103
| | | | | | | This should fix the stack-use-after-scope reported by the asan buildbots after revision 328493. llvm-svn: 328499
* [X86][Btver2] Add (V)SQRTPD/(V)SQRTSD costsSimon Pilgrim2018-03-262-8/+8
| | | | | | The xmm sd/pd versions were using the WriteFSQRT default which is modelled on sqrtss/sqrtps llvm-svn: 328497
* [llvm-mca] Add a flag -instruction-info to enable/disable the instruction ↵Andrea Di Biagio2018-03-261-0/+23
| | | | | | info view. llvm-svn: 328493
* [X86][Btver2] Double the AGU and schedule pipe resources for YMMSimon Pilgrim2018-03-262-105/+105
| | | | | | Both the AGUs and schedule pipes are double pumped for 256-bit instructions as well as the functional units which we already model. llvm-svn: 328491
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-2610-706/+707
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
* [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function ↵Simon Pilgrim2018-03-232-35/+35
| | | | | | unit llvm-svn: 328343
* [X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unitSimon Pilgrim2018-03-233-298/+298
| | | | | | Add missing non-VEX and (V)PMOVMSKB instructions to the pattern llvm-svn: 328338
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