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* [llvm-mca] report an error if the assembly sequence contains an unsupported ↵Andrea Di Biagio2018-07-091-0/+6
| | | | | | | | | | | | | instruction. This is a short-term fix for PR38093. For now, we llvm::report_fatal_error if the instruction builder finds an unsupported instruction in the instruction stream. We need to revisit this fix once we start addressing PR38101. Essentially, we need a better framework for error handling. llvm-svn: 336543
* [MCA][X86][NFC] Add BSF/BSR resource testsRoman Lebedev2018-07-0810-10/+400
| | | | | | | | | | | | Reviewers: RKSimon, andreadb, courbet Reviewed By: RKSimon Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48997 llvm-svn: 336510
* [llvm-objcopy] Add support for static librariesAlexander Shaposhnikov2018-07-064-1/+169
| | | | | | | | | | | This diff adds support for handling static libraries to llvm-objcopy and llvm-strip. Test plan: make check-all Differential revision: https://reviews.llvm.org/D48413 llvm-svn: 336455
* [llvm-mca] improve the instruction issue logic implemented by the Scheduler.Andrea Di Biagio2018-07-063-60/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the Scheduler heuristic used to select the next instruction to issue to the pipelines. The motivating example is test X86/BtVer2/add-sequence.s, for which llvm-mca wrongly reported an estimated IPC of 1.50. According to perf, the actual IPC for that test should have been ~2.00. It turns out that an IPC of 2.00 for test add-sequence.s cannot possibly be predicted by a Scheduler that only prioritizes instructions based on their "age". A similar issue also affected test X86/BtVer2/dependent-pmuld-paddd.s, for which llvm-mca wrongly estimated an IPC of 0.84 instead of an IPC of 1.00. Instructions in the ReadyQueue are now ranked based on two factors: - The "age" of an instruction. - The number of unique users of writes associated with an instruction. The new logic still prioritizes older instructions over younger instructions to minimize the pressure on the reorder buffer. However, the number of users of an instruction now also affects the overall rank. This potentially increases the ability of the Scheduler to extract instruction level parallelism. This patch fixes the problem with the wrong IPC reported for test add-sequence.s and test dependent-pmuld-paddd.s. llvm-svn: 336420
* Reapply: "objdump: Support newer ObjC image info flags"Dave Lee2018-07-061-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for two additional ObjC image info flags: `IS_SIMULATED` and `HAS_CATEGORY_CLASS_PROPERTIES`. `IS_SIMULATED` indicates a Mach-O binary built for iOS simulator. `HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler that supports class properties in categories. Reviewers: enderby, compnerd Reviewed By: compnerd Subscribers: keith, llvm-commits Differential Revision: https://reviews.llvm.org/D48568 llvm-svn: 336411
* Revert "objdump: Support newer ObjC image info flags"Dave Lee2018-07-061-7/+0
| | | | | | This reverts commit 8c4cc472e7a67bd3b2b20cc4cf32d31af29bc7e9. llvm-svn: 336402
* objdump: Support newer ObjC image info flagsDave Lee2018-07-051-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for two additional ObjC image info flags: `IS_SIMULATED` and `HAS_CATEGORY_CLASS_PROPERTIES`. `IS_SIMULATED` indicates a Mach-O binary built for iOS simulator. `HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler that supports class properties in categories. Reviewers: enderby, compnerd Reviewed By: compnerd Subscribers: keith, llvm-commits Differential Revision: https://reviews.llvm.org/D48568 llvm-svn: 336399
* [llvm-objdump] Removed archive-headers-disas testPaul Semel2018-07-051-29/+0
| | | | | | | | This test is failing because of the disas part. For the moment, I will juste remove it. I will add it again tomorrow with a proper fix. llvm-svn: 336370
* [llvm-objcopy] Fix timezone dependant testsPaul Semel2018-07-052-18/+18
| | | | llvm-svn: 336363
* [llvm-objdump] Add --archive-headers (-a) optionPaul Semel2018-07-053-0/+50
| | | | llvm-svn: 336357
* [X86][BtVer2][MCA][NFC] Add CMPEQ dependency-breaking one-idioms testsRoman Lebedev2018-07-042-0/+157
| | | | | | | | | | | | | | | | | | | Summary: As per `Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions)`, these, like zero-idioms, are dependency-breaking, although they produce ones and still consume resources. FIXME: as discussed in D48877, llvm-mca handling is broken for these. Reviewers: andreadb Reviewed By: andreadb Subscribers: gbedwell, RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D48876 llvm-svn: 336292
* [llvm-objdump] Add --file-headers (-f) optionPaul Semel2018-07-044-0/+63
| | | | llvm-svn: 336284
* NFC - Various typo fixes in testsGabor Buella2018-07-041-5/+5
| | | | llvm-svn: 336268
* Remove absolute path in testTeresa Johnson2018-07-021-1/+1
| | | | | | | My test change in r336148 accidentally included an absolute path, clean that up to fix bot failures. llvm-svn: 336151
* [ThinLTO] Fix printing of module paths for distributed backend indexesTeresa Johnson2018-07-021-0/+10
| | | | | | | | | | | | | | | | Summary: In the individual index files emitted for distributed ThinLTO backends, the module path ids are not contiguous. Assign slots to module paths in order to handle this better and also to get contiguous numbering in the summary assembly. Reviewers: davidxl, dexonsmith Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, steven_wu Differential Revision: https://reviews.llvm.org/D48698 llvm-svn: 336148
* Replace unused output filenames with /dev/null in testsFangrui Song2018-07-027-7/+7
| | | | | | Similar to rLLD336129 llvm-svn: 336131
* nm: Add -no-weak flag for hiding weak symbolsDave Lee2018-07-021-0/+1
| | | | | | | | | | | | | | | | | | Summary: This adds a new -no-weak flag to nm to hide weak symbols in its output. This also adds a -W alias for this which is analogous to -U. Patch by Keith Smiley Reviewers: kastiglione, enderby, compnerd Reviewed By: kastiglione Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48751 llvm-svn: 336126
* Revert "[llvm-readobj] Fix printing format"Paul Semel2018-07-011-8/+0
| | | | | | | There is a problem with the formatting on windows build. I need to investigate on this. llvm-svn: 336061
* [llvm-readobj] Fix printing formatPaul Semel2018-07-011-0/+8
| | | | | | | | | | | | We were printing every character, even those that weren't printable. It doesn't really make sense for this option. The string content was sticked to its address, added two spaces in between. Differential Revision: https://reviews.llvm.org/D48271 llvm-svn: 336058
* [dsymutil] Make the CachedBinaryHolder the defaultJonas Devlieghere2018-06-291-6/+6
| | | | | | | | Replaces all uses of the old binary holder with its cached variant. Differential revision: https://reviews.llvm.org/D48770 llvm-svn: 335991
* Require x86 for this test.Sterling Augustine2018-06-281-0/+1
| | | | llvm-svn: 335939
* [llvm-readobj] Add experimental support for SHT_RELR sectionsJake Ehrlich2018-06-283-0/+182
| | | | | | | | | | | | | | | This change adds experimental support for SHT_RELR sections, proposed here: https://groups.google.com/forum/#!topic/generic-abi/bX460iggiKg Definitions for the new ELF section type and dynamic array tags, as well as the encoding used in the new section are all under discussion and are subject to change. Use with caution! Author: rahulchaudhry Differential Revision: https://reviews.llvm.org/D47919 llvm-svn: 335922
* Some targets don't have lld built, so just use a binary copySterling Augustine2018-06-282-3/+1
| | | | | | of the input file. llvm-svn: 335908
* Handle absolute symbols as branch targets in disassembly.Sterling Augustine2018-06-281-0/+4
| | | | | | https://reviews.llvm.org/D48554 llvm-svn: 335903
* [llvm-mca][x86] Add FMA4 resource testsSimon Pilgrim2018-06-281-0/+349
| | | | | | We should be ensuring we have (near) complete test coverage of instructions, at least for the generic model. llvm-svn: 335870
* [llvm-mca][x86] Add 3dnow! resource testsSimon Pilgrim2018-06-281-0/+208
| | | | | | We should be ensuring we have (near) complete test coverage of instructions, at least for the generic model. llvm-svn: 335869
* Move `REQUIRES:` line to the topFangrui Song2018-06-261-1/+1
| | | | llvm-svn: 335635
* ARM: add binary file git swallowed.Tim Northover2018-06-262-0/+0
| | | | | | Should fix bots. llvm-svn: 335596
* ARM: diagnose unpredictable IT instructionsTim Northover2018-06-261-0/+10
| | | | | | | | | | | IT instructions are allowed to have the 'AL' predicate, but it must never result in an 'NV' predicated instruction. Essentially this means that all branches must be 't' rather than 'e' if the predicate is 'AL'. This patch adds a diagnostic for this during assembly (error because parsing hits an assertion if allowed to continue) and an annotation during disassembly. llvm-svn: 335593
* [SelectionDAG] Remove debug locations from ConstantSD(FP)NodesVedant Kumar2018-06-251-4/+4
| | | | | | | | | | | | | | | | | | This removes debug locations from ConstantSDNode and ConstantSDFPNode. When this kind of node is materialized we no longer create a line table entry which jumps back to the constant's first point of use. This makes single-stepping behavior smoother, and it matches the model used by IR, where Constants have no locations. See this thread for more context: http://lists.llvm.org/pipermail/llvm-dev/2018-June/124164.html I'd like to handle constant BuildVectorSDNodes and to try to eliminate passing SDLocs to SelectionDAG::getConstant*() in follow-up commits. Differential Revision: https://reviews.llvm.org/D48468 llvm-svn: 335497
* [llvm-mt] Use WithColor for printing errors.Jonas Devlieghere2018-06-233-5/+5
| | | | | | Use the WithColor helper from support to print errors. llvm-svn: 335416
* [LIT] Enable testing of LLVM gold plugin on Mac OS XEugene Leviant2018-06-207-2/+8
| | | | | | Differential revision: https://reviews.llvm.org/D48350 llvm-svn: 335136
* [llvm-mca][X86] Teach how to identify register writes that implicitly clear ↵Andrea Di Biagio2018-06-207-167/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the upper portion of a super-register. This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
* [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.Roman Lebedev2018-06-202-0/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: First off: i do not have any access to that processor, so this is purely theoretical, no benchmarks. I have been looking into b**d**ver2 scheduling profile, and while cross-referencing the existing b**t**ver2, znver1 profiles, and the reference docs (`Software Optimization Guide for AMD Family {15,16,17}h Processors`), i have noticed that only b**t**ver2 scheduling profile specifies these. Also, there is no mca test coverage. Reviewers: RKSimon, craig.topper, courbet, GGanesh, andreadb Reviewed By: GGanesh Subscribers: gbedwell, vprasad, ddibyend, shivaram, Ashutosh, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D47676 llvm-svn: 335099
* [X86] Fix r335097Clement Courbet2018-06-201-1/+5
| | | | | | Missed `Generic` test in llvm-mca. llvm-svn: 335098
* [X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet2018-06-2010-9/+85
| | | | | | | | | | | | | | | Summary: I ran llvm-exegesis on SKX, SKL, BDW, HSW, SNB. Atom is from Agner and SLM is a guess. I've left AMD processors alone. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48079 llvm-svn: 335097
* [MCA][NFC] Add generic XOP resource testsRoman Lebedev2018-06-191-0/+534
| | | | | | | | | | | | | | | | | | | | | Summary: Based on * [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]], * [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]], * https://en.wikipedia.org/wiki/XOP_instruction_set Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4], for which currently llvm has no scheduling profiles. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: RKSimon Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48264 llvm-svn: 335034
* [MCA][NFC] Add generic TBM resource testsRoman Lebedev2018-06-191-0/+169
| | | | | | | | | | | | | | | | | | | Summary: Based on https://support.amd.com/TechDocs/24594.pdf, https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation) Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4], for which currently llvm has no scheduling profiles. Reviewers: RKSimon, craig.topper, simark, andreadb Reviewed By: RKSimon Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48252 llvm-svn: 335033
* [llvm-mca] Use an ordered map to collect hardware statistics. NFC.Andrea Di Biagio2018-06-186-5/+6
| | | | | | | Histogram entries are now ordered by key. This should improves their readability when statistics are printed. llvm-svn: 334961
* [llvm-mca] Add tests for XOP and AVX512 instructions that implicitly clear ↵Andrea Di Biagio2018-06-185-0/+430
| | | | | | | | | | | | | | | | | | | the upper portion of a super-register. When the destination register of a XOP instruction is an XMM register, bits [255:128] of the corresponding YMM register are cleared. When the destination register of a EVEX encoded instruction is an XMM/YMM register, the upper bits of the corresponding ZMM are cleared. On processors that feature AVX512, a write to an XMM registers always clears the upper portion of the corresponding ZMM register if the instruction is VEX or EVEX encoded. These new tests show some interesting cases which aren't correctly analyzed by llvm-mca. The lack of knowledge related to the implicit update on the super-registers is addressed by D48225. llvm-svn: 334945
* [X86] Fix NOOP sched overrides on BDW/HSW/SKL.Clement Courbet2018-06-183-31/+31
| | | | | | | | | | | | Summary: Noop certainly does not use resources. Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits, gchatelet Differential Revision: https://reviews.llvm.org/D48028 llvm-svn: 334927
* [llvm-mca][X86] Add some avx512f/avx512vl resource test placeholdersSimon Pilgrim2018-06-172-0/+514
| | | | | | There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings llvm-svn: 334907
* [llvm-mca][x86] Add Generic cpu resource testsSimon Pilgrim2018-06-1521-0/+9934
| | | | | | | | Added a Generic x86 cpu set of resource tests to allow us to check all ISAs. We currently use SandyBridge as our generic CPU model, but it's better if we actually duplicate these tests for if/when we change the model, it also means we don't end up polluting the SandyBridge folder with tests for ISAs it doesn't support. llvm-svn: 334853
* [MCA] Add -summary-view optionRoman Lebedev2018-06-154-72/+18
| | | | | | | | | | | | | | | | | | | Summary: While that is indeed a quite interesting summary stat, there are cases where it does not really add anything other than consuming extra lines. Declutters the output of D48190. Reviewers: RKSimon, andreadb, courbet, craig.topper Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48209 llvm-svn: 334833
* [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-statsRoman Lebedev2018-06-152-0/+134
| | | | | | | | | | | | | | | | Summary: There does not seem to be any other tests for this. Split off from D47676. Reviewers: RKSimon, craig.topper, courbet, andreadb Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48190 llvm-svn: 334832
* [llvm-mca] Add tests for instructions that implicitly clear the upper ↵Andrea Di Biagio2018-06-142-0/+176
| | | | | | | | | | | | | portion of a super-register. On x86-64, a write to register EAX implicitly clears the upper half or RAX. 128-bit AVX instructions clear the upper 128-bit of the YMM register that aliases the XMM definition register. llvm-mca doesn't know about register writes that implicitly clear the upper portion of an aliasing super-register. This issue will be fixed in a future patch. llvm-svn: 334742
* [llvm-mca] Add another test for partial register stalls.Andrea Di Biagio2018-06-141-0/+43
| | | | | | | | | This test checks that a physical register is correctly allocated for the partial write to register BX. The ADD instruction has to wait for the write to RBX (and BX) before being executed. llvm-svn: 334730
* [llvm-mca] Fixed a bug in the logic that checks if a memory operation is ↵Andrea Di Biagio2018-06-131-0/+41
| | | | | | | | | | | | | | | ready to execute. Fixes PR37790. In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a load (or store) as "ready to execute" effectively bypassing older memory barrier instructions. To reproduce this bug, the memory barrier must be the first instruction in the input assembly sequence, and it doesn't have to perform any register writes. llvm-svn: 334633
* [DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entriesPavel Labath2018-06-131-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This method was not correct for entries in DWO files as it assumed it could just add up the CU and DIE offsets to get the absolute DIE offset. This is not correct for the DWO files, as here the CU offset will reference the skeleton unit, whereas the DIE offset will be the offset in the full unit in the DWO file. Unfortunately, this means that we are not able to determine the absolute DIE offset using the information in the .debug_names section alone, which means we have to offload some of this work to the users of this class. To demonstrate how this can be done, I've added/fixed the ability to lookup entries using accelerator tables in DWO files in llvm-dwarfdump. To make this happen, I've needed to make two extra changes in other classes: - made the DWARFContext method to lookup a CU based on the section offset public. I've needed this functionality to lookup a CU, and this seems like a useful thing in general. - made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the DWOId was filled in only if the root DIE happened to be parsed before we called the accessor. Since the lazy parsing is supposed to happen under the hood, calling extractDIEsIfNeeded seems appropriate. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D48009 llvm-svn: 334578
* [X86] Fix skylake server scheduling info.Clement Courbet2018-06-1110-721/+721
| | | | | | | | | | | | | | Summary: This fixes most of the scheduling info for SKX vector operations. I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM. The before/after llvm-exegesis analysis are in the phabricator diff. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47721 llvm-svn: 334407
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