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* [llvm-mca][x86] Remove addsubpd from SSE2 testsSimon Pilgrim2018-05-079-72/+9
| | | | llvm-svn: 331678
* [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classesSimon Pilgrim2018-05-072-6/+6
| | | | | | | | Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-071-37/+37
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.Simon Pilgrim2018-05-071-17/+17
| | | | | | Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. llvm-svn: 331645
* [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM ↵Simon Pilgrim2018-05-072-50/+50
| | | | | | | | and YMM/ZMM instructions. This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values. llvm-svn: 331643
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-0711-63/+63
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-044-12/+12
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-042-18/+18
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-031-3/+3
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* [X86][SNB] Fix scheduling of MMX integer multiply instructions.Simon Pilgrim2018-05-024-8/+8
| | | | | | The entries were being bound to the wrong class. llvm-svn: 331388
* [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.Clement Courbet2018-05-021-2/+2
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331356
* [llvm-mca] Regenerate test Atom/resources-sse3.s. NFCAndrea Di Biagio2018-04-301-47/+41
| | | | | | Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom. llvm-svn: 331170
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-307-0/+3787
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-298-8/+1184
| | | | llvm-svn: 331144
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-298-8/+3016
| | | | llvm-svn: 331140
* [llvm-mca][X86] Add double shift resource tests to all relevant modelsSimon Pilgrim2018-04-288-8/+608
| | | | llvm-svn: 331109
* [llvm-mca][X86] Add shift/rotate resource tests to all relevant modelsSimon Pilgrim2018-04-288-0/+4386
| | | | | | I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch llvm-svn: 331108
* [llvm-mca][X86] Updated fma3 tests after rL330820Simon Pilgrim2018-04-252-10/+10
| | | | llvm-svn: 330822
* [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.Andrea Di Biagio2018-04-251-1/+0
| | | | llvm-svn: 330809
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-242-6/+6
| | | | | | This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-241-5/+5
| | | | | | Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887) llvm-svn: 330737
* [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latenciesSimon Pilgrim2018-04-241-11/+5
| | | | | | These are stores, not loads, so don't need to account for load latency. llvm-svn: 330735
* [X86][IVB] Add F16C resource tests.Simon Pilgrim2018-04-241-0/+58
| | | | | | Note this is IvyBridge (which shares the model) NOT SandyBridge. llvm-svn: 330734
* [llvm-mca] Default the output asm dialect used by the instruction printer to ↵Andrea Di Biagio2018-04-241-0/+37
| | | | | | | | | | | | | | | | the input asm dialect. The instruction printer used by llvm-mca to generate the performance report now defaults the output assembly format to the format used for the input assembly file. On x86, the asm format can be either AT&T or Intel, depending on the presence/absence of directive `.intel_syntax`. Users can still specify a different assembly dialect with the command line flag -output-asm-variant=<uint>. llvm-svn: 330733
* [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-242-4/+4
| | | | llvm-svn: 330720
* [X86] Add vector element insertion/extraction scheduler classesSimon Pilgrim2018-04-242-10/+10
| | | | | | | | | | | | Split off pinsr/pextr and extractps instructions. (Mostly) fixes PR36887. Note: It might be worth adding a WriteFInsertLd class as well in the future. Differential Revision: https://reviews.llvm.org/D45929 llvm-svn: 330714
* [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant modelsSimon Pilgrim2018-04-2225-0/+2322
| | | | | | The SandyBridge BMI tests are actually run on IvyBridge as that's the first lowest CPU that actually support the ISAs (but still use the SandyBridge model). llvm-svn: 330556
* [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.Simon Pilgrim2018-04-222-28/+30
| | | | | | This also fixes some of the ReadAfterLd issues due to InstRW. llvm-svn: 330544
* [llvm-mca][X86] Add POPCNT resource testSimon Pilgrim2018-04-222-0/+108
| | | | llvm-svn: 330540
* [llvm-mca][X86] Add AVX2 resource testsSimon Pilgrim2018-04-215-0/+5387
| | | | llvm-svn: 330512
* [llvm-mca][X86] Add SSE resource tests to all modelsSimon Pilgrim2018-04-2135-0/+13352
| | | | llvm-svn: 330506
* [llvm-mca][X86] Add MMX resource testsSimon Pilgrim2018-04-216-0/+2376
| | | | llvm-svn: 330502
* [llvm-mca][X86] Add X87 resource testsSimon Pilgrim2018-04-218-0/+4194
| | | | llvm-svn: 330499
* [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge testsSimon Pilgrim2018-04-209-0/+2733
| | | | llvm-svn: 330486
* [llvm-mca][X86] Add prefetch instruction resource testsSimon Pilgrim2018-04-191-1/+14
| | | | llvm-svn: 330371
* [llvm-mca][FMA] Add FMA resource testsSimon Pilgrim2018-04-195-0/+3522
| | | | llvm-svn: 330366
* [llvm-mca][X86] Add resource test for every out-of-order scheduler modelSimon Pilgrim2018-04-197-0/+14536
| | | | | | | | | | I've copied and regenerated a resource file from btver2 to every x86 scheduler model supported by llvm-mca so we have at least some basic coverage. For most this has been the avx1 tests, but for silvermont I've used sse42 as thats the latest it supports. More will be added later. llvm-svn: 330352
* [llvm-mca][X86] Add mmx instruction to btver2 resource testsSimon Pilgrim2018-04-193-8/+569
| | | | | | Useful to see scheduler class deltas against xmm equivalents llvm-svn: 330335
* [llvm-mca][X86] Add mmx versions of SSSE3 instructionsSimon Pilgrim2018-04-182-23/+135
| | | | | | Move PABS instructions incorrectly tested under SSE2 llvm-svn: 330295
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-1831-138/+989
| | | | | | | | | | | This script can be used to regenerate tests in the test/tools/llvm-mca directory (PR36904). Regenerated a number of tests using the pattern: test/tools/llvm-mca/*/*/*.s Differential Revision: https://reviews.llvm.org/D45369 llvm-svn: 330246
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-171-2/+2
| | | | llvm-svn: 330204
* [llvm-mca] Ensure that instructions with a schedule read-advance are always ↵Andrea Di Biagio2018-04-131-0/+44
| | | | | | | | | | | | | | issued in the right order. Normally, the Scheduler prioritizes older instructions over younger instructions during the instruction issue stage. In one particular case where a dependent instruction had a schedule read-advance associated to one of the input operands, this rule was not correctly applied. This patch fixes the issue and adds a test to verify that we don't regress that particular case. llvm-svn: 330032
* [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.Andrea Di Biagio2018-04-111-0/+56
| | | | | | Also, removed flag -verbose in favor of flag -retire-stats. llvm-svn: 329794
* [llvm-mca] Move the logic that prints scheduler statistics from ↵Andrea Di Biagio2018-04-111-2/+26
| | | | | | | | BackendStatistics to its own view. Added flag -scheduler-stats to print scheduler related statistics. llvm-svn: 329792
* [llvm-mca] Move the logic that prints dispatch unit statistics from ↵Andrea Di Biagio2018-04-105-5/+5
| | | | | | | | | | | BackendStatistics to its own view. This patch moves the logic that collects and analyzes dispatch events to the DispatchStatistics view. Added flag -dispatch-stats to print statistics related to the dispatch logic. llvm-svn: 329708
* [llvm-mca] Increase the default number of iterations to 100.Andrea Di Biagio2018-04-104-55/+144
| | | | llvm-svn: 329694
* Reapply "[llvm-mca] Do not separate iterations with a newline in the ↵Andrea Di Biagio2018-04-106-17/+18
| | | | | | | | timeline view." This reapplies r329403 with a fix for the floating point rounding issue. llvm-svn: 329680
* [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)Andrea Di Biagio2018-04-097-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to parse code comments in search for special "markers" used to select regions of code. Example: # LLVM-MCA-BEGIN My Code Region .... # LLVM-MCA-END The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an AsmCommentConsumer) the parsing of code comments to search for begin/end code region markers. A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new region of code. A comment starting with substring "LLVM-MCA-END" marks the end of the last region. This implementation doesn't allow regions to overlap. Each region can have a optional description; internally, each region is identified by a range of source code locations (SMLoc). MCInst objects are added to a region R only if the source location for the MCInst is in the range of locations specified by R. By default, the tool allocates an implicit "Default" code region which contains every source location. See new tests llvm-mca-marker-*.s for a few examples. A new Backend object is created for every region. So, the analysis is conducted on every parsed code region. The final report is the union of the reports generated for every code region. Note that empty regions are skipped. Special "[#] Code Region - ..." strings are used in the report to mark the portion which is specific to a code region only. For example, see llvm-mca-markers-5.s. Differential Revision: https://reviews.llvm.org/D45433 llvm-svn: 329590
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the ↵Hans Wennborg2018-04-096-18/+17
| | | | | | | | | | | | timeline view." This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251 > Also, update a few tests to minimize the diff in D45369. > No functional change intended. llvm-svn: 329569
* [X86][Btver2] Add vector extract costsSimon Pilgrim2018-04-083-30/+30
| | | | llvm-svn: 329524
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