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* [X86] Add GPR<->XMM Schedule TagsSimon Pilgrim2018-05-181-5/+5
| | | | | | | | | | BtVer2 - fix NumMicroOp and account for the Lat+6cy GPR->XMM and Lat+1cy XMm->GPR delays (see rL332737) The high number of MOVD/MOVQ equivalent instructions meant that there were a number of missed patterns in SNB/Znver1: SNB - add missing GPR<->MMX costs (taken from Agner / Intel AOM) Znver1 - add missing GPR<->XMM MOVQ costs (taken from Agner) llvm-svn: 332745
* [llvm-mca][X86] Add CMOV test filesSimon Pilgrim2018-05-171-0/+328
| | | | llvm-svn: 332622
* [llvm-mca][X86] Add ADX test filesSimon Pilgrim2018-05-171-0/+60
| | | | llvm-svn: 332595
* [X86] Fix typo in instregex for CVTSI642SDrrSimon Pilgrim2018-05-162-4/+4
| | | | llvm-svn: 332510
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-1618-5522/+5522
| | | | llvm-svn: 332447
* [llvm-mca][x86] Add F16C instruction testsSimon Pilgrim2018-05-151-0/+62
| | | | llvm-svn: 332347
* [llvm-mca][X86] Add missing SSE4A test fileSimon Pilgrim2018-05-141-0/+55
| | | | llvm-svn: 332270
* [llvm-mca][x86] Add scalar nt-store instruction testsSimon Pilgrim2018-05-141-1/+8
| | | | llvm-svn: 332262
* [llvm-mca][x86] Add and/not/or/xor instruction testsSimon Pilgrim2018-05-141-1/+308
| | | | llvm-svn: 332257
* [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)Simon Pilgrim2018-05-081-33/+33
| | | | | | | I've created the necessary classes but there are still a lot of overrides that need cleaning up. NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides. llvm-svn: 331767
* [llvm-mca][x86] Add div/idiv, mul/imul and inc/dec/neg/nop instruction testsSimon Pilgrim2018-05-081-1/+255
| | | | llvm-svn: 331765
* [llvm-mca][x86] Remove addsubpd from SSE2 testsSimon Pilgrim2018-05-071-8/+1
| | | | llvm-svn: 331678
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-071-37/+37
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.Simon Pilgrim2018-05-071-17/+17
| | | | | | Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. llvm-svn: 331645
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-074-42/+42
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-041-3/+3
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-031-3/+3
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-291-1/+148
| | | | llvm-svn: 331144
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-291-1/+377
| | | | llvm-svn: 331140
* [llvm-mca][X86] Add double shift resource tests to all relevant modelsSimon Pilgrim2018-04-281-1/+76
| | | | llvm-svn: 331109
* [llvm-mca][X86] Add shift/rotate resource tests to all relevant modelsSimon Pilgrim2018-04-281-0/+550
| | | | | | I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch llvm-svn: 331108
* [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant modelsSimon Pilgrim2018-04-224-0/+374
| | | | | | The SandyBridge BMI tests are actually run on IvyBridge as that's the first lowest CPU that actually support the ISAs (but still use the SandyBridge model). llvm-svn: 330556
* [llvm-mca][X86] Add AVX2 resource testsSimon Pilgrim2018-04-211-0/+1079
| | | | llvm-svn: 330512
* [llvm-mca][X86] Add SSE resource tests to all modelsSimon Pilgrim2018-04-216-0/+2254
| | | | llvm-svn: 330506
* [llvm-mca][X86] Add MMX resource testsSimon Pilgrim2018-04-211-0/+398
| | | | llvm-svn: 330502
* [llvm-mca][X86] Add X87 resource testsSimon Pilgrim2018-04-211-0/+526
| | | | llvm-svn: 330499
* [llvm-mca][FMA] Add FMA resource testsSimon Pilgrim2018-04-191-0/+706
| | | | llvm-svn: 330366
* [llvm-mca][X86] Add resource test for every out-of-order scheduler modelSimon Pilgrim2018-04-191-0/+2408
I've copied and regenerated a resource file from btver2 to every x86 scheduler model supported by llvm-mca so we have at least some basic coverage. For most this has been the avx1 tests, but for silvermont I've used sse42 as thats the latest it supports. More will be added later. llvm-svn: 330352
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