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* [NFC][InstCombine] onehot_merge.ll: add last few tests in the state they ↵Roman Lebedev2019-07-031-0/+39
| | | | | | regress to in D62818 llvm-svn: 365056
* [InstCombine] Y - ~X --> X + Y + 1 fold (PR42457)Roman Lebedev2019-07-031-7/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: I *think* we'd want this new variant, because we obviously have better handling for `add` as compared to `sub`/`not`. https://rise4fun.com/Alive/WMn Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]] Reviewers: spatel, nikic, huihuiz, efriedma Reviewed By: spatel Subscribers: RKSimon, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63992 llvm-svn: 365011
* [SimplifyLibCalls] powf(x, sitofp(n)) -> powi(x, n)David Bolvansky2019-07-022-76/+343
| | | | | | | | | | | | | | | | | | | Summary: Partially solves https://bugs.llvm.org/show_bug.cgi?id=42190 Reviewers: spatel, nikic, efriedma Reviewed By: efriedma Subscribers: efriedma, nikic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63038 llvm-svn: 364940
* [InstCombine] Shift amount reassociation: fixup constantexpr handling (PR42484)Roman Lebedev2019-07-021-0/+15
| | | | | | | | | | | | | | | I was actually wondering if there was some nicer way than m_Value()+cast, but apparently what i was really "subconsciously" thinking about was correctness issue. hasNoUnsignedWrap()/hasNoUnsignedWrap() exist for Instruction, not for BinaryOperator, so let's just use m_Instruction(), thus both avoiding a cast, and a crash. Fixes https://bugs.llvm.org/show_bug.cgi?id=42484, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15587 llvm-svn: 364915
* [NFC][InstCombine] Revisit tests for "redundant shift input masking" (PR42456)Roman Lebedev2019-07-021-10/+30
| | | | llvm-svn: 364897
* [NFC][InstCombine] Add tests for "redundant shift input masking" (PR42456)Roman Lebedev2019-07-021-0/+229
| | | | | | | https://bugs.llvm.org/show_bug.cgi?id=42456 https://rise4fun.com/Alive/Vf1p llvm-svn: 364894
* [InstCombine][NFCI] Update test cases in onehot_merge.llHuihui Zhang2019-07-011-8/+46
| | | | | | | | | | | | | | | | Use both one bit and signbit shifting to check for one bit merge. Reviewers: lebedev.ri, spatel, efriedma, craig.topper Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63903 llvm-svn: 364857
* [InstCombine] reduce more checks for power-of-2-or-zero using ctpopSanjay Patel2019-07-011-39/+23
| | | | | | | | | Extends the transform from: rL364341 ...to include another (more common?) pattern that tests whether a value is a power-of-2 (including or excluding zero). llvm-svn: 364856
* [NFC][InstCombine] More commutative tests for "shift direction in bittest" ↵Roman Lebedev2019-07-011-16/+61
| | | | | | | | | (PR42466) 'and' is commutative, if we don't want to touch shift-of-const, we still need to check the other hand of 'and'. llvm-svn: 364844
* [NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466)Roman Lebedev2019-07-011-0/+234
| | | | | | | https://rise4fun.com/Alive/8O1 https://bugs.llvm.org/show_bug.cgi?id=42466 llvm-svn: 364824
* [InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459)Roman Lebedev2019-07-012-27/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To be noted, this pattern is not unhandled by instcombine per-se, it is somehow does end up being folded when one runs opt -O3, but not if it's just -instcombine. Regardless, that fold is indirect, depends on some other folds, and is thus blind when there are extra uses. This does address the regression being exposed in D63992. https://godbolt.org/z/7DGltU https://rise4fun.com/Alive/EPO0 Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42459 | PR42459 ]] Reviewers: spatel, nikic, huihuiz Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63993 llvm-svn: 364792
* [InstCombine] Shift amount reassociation in bittest (PR42399)Roman Lebedev2019-07-011-108/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Given pattern: `icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0` we should move shifts to the same hand of 'and', i.e. rewrite as `icmp eq/ne (and (x shift (Q+K)), y), 0` iff `(Q+K) u< bitwidth(x)` It might be tempting to not restrict this to situations where we know we'd fold two shifts together, but i'm not sure what rules should there be to avoid endless combine loops. We pick the same shift that was originally used to shift the variable we picked to shift: https://rise4fun.com/Alive/6x1v Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42399 | PR42399]]. Reviewers: spatel, nikic, RKSimon Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63829 llvm-svn: 364791
* [NFC][InstCombine] Better commutative tests for "shift amount reassociation ↵Roman Lebedev2019-07-011-30/+144
| | | | | | | | | | | | in bittest" pattern. As discussed in https://reviews.llvm.org/D63829 *if* *both* shifts are one-use, we'd most likely want to produce `lshr`, and not rely on ordering. Also, there should likely be a *separate* fold to do this reordering. llvm-svn: 364772
* [NFC][InstCombine] Improve test coverage for ((~x) + y) + 1 -> y - x fold ↵Roman Lebedev2019-07-011-6/+46
| | | | | | | | fold (PR42459) So we indeed to have this fold, but only if +1 is not the last operation.. llvm-svn: 364764
* [NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold fold (PR42459)Roman Lebedev2019-07-011-0/+184
| | | | | | | | | | | | | To be noted, this pattern is not unhandled by instcombine per-se, it is somehow does end up being folded when one runs opt -O3, but not if it's just -instcombine. Regardless, that fold is indirect, depends on some other folds, and is thus blind when there are extra uses. https://bugs.llvm.org/show_bug.cgi?id=42459 https://rise4fun.com/Alive/EPO0 llvm-svn: 364749
* [NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold (PR42457)Roman Lebedev2019-07-011-0/+94
| | | | | | | https://bugs.llvm.org/show_bug.cgi?id=42457 https://rise4fun.com/Alive/iFhE llvm-svn: 364739
* [InstCombine] Omit 'urem' where possibleRoman Lebedev2019-07-011-9/+4
| | | | | | | | This was added in D63390 / rL364286 to backend, but it makes sense to also handle it in middle-end. https://rise4fun.com/Alive/Zsln llvm-svn: 364738
* [NFC][InstCombine] Copy test for omit urem when possible from TargetLoweringRoman Lebedev2019-07-011-0/+171
| | | | | | | Was added in D63390 / rL364286 to backend, but it makes sense to also handle it here. https://rise4fun.com/Alive/Zsln llvm-svn: 364737
* [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsicsSanjay Patel2019-06-301-12/+8
| | | | | | | | | | | | This is the opposite direction of D62158 (we have to choose 1 form or the other). Now that we have FMF on the select, this becomes more palatable. And the benefits of having a single IR instruction for this operation (less chances of missing folds based on extra uses, etc) overcome my previous comments about the potential advantage of larger pattern matching/analysis. Differential Revision: https://reviews.llvm.org/D62414 llvm-svn: 364721
* [InstCombine] canonicalize fmin/fmax to LLVM intrinsics minnum/maxnumSanjay Patel2019-06-293-55/+46
| | | | | | | | | | | | | | This transform came up in D62414, but we should deal with it first. We have LLVM intrinsics that correspond exactly to libm calls (unlike most libm calls, these libm calls never set errno). This holds without any fast-math-flags, so we should always canonicalize to those intrinsics directly for better optimization. Currently, we convert to fcmp+select only when we have FMF (nnan) because fcmp+select does not preserve the semantics of the call in the general case. Differential Revision: https://reviews.llvm.org/D63214 llvm-svn: 364714
* [InstCombine] Shift amount reassociation (PR42391)Roman Lebedev2019-06-291-48/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Given pattern: `(x shiftopcode Q) shiftopcode K` we should rewrite it as `x shiftopcode (Q+K)` iff `(Q+K) u< bitwidth(x)` This is valid for any shift, but they must be identical. * https://rise4fun.com/Alive/9E2 * exact on both lshr => exact https://rise4fun.com/Alive/plHk * exact on both ashr => exact https://rise4fun.com/Alive/QDAA * nuw on both shl => nuw https://rise4fun.com/Alive/5Uk * nsw on both shl => nsw https://rise4fun.com/Alive/0plg Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42391 | PR42391]]. Reviewers: spatel, nikic, RKSimon Reviewed By: nikic Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63812 llvm-svn: 364712
* [NFC][InstCombine] Shift amount reassociation: revisit flag preservation testsRoman Lebedev2019-06-281-12/+26
| | | | llvm-svn: 364657
* [NFC][InstCombine] Shift amount reassociation: add flag preservation testRoman Lebedev2019-06-281-10/+55
| | | | | | | | | | | | | As discussed in https://reviews.llvm.org/D63812#inline-569870 * exact on both lshr => exact https://rise4fun.com/Alive/plHk * exact on both ashr => exact https://rise4fun.com/Alive/QDAA * nuw on both shl => nuw https://rise4fun.com/Alive/5Uk * nsw on both shl => nsw https://rise4fun.com/Alive/0plg So basically if the same flag is set on both original shifts -> set it on new shift. Don't think we can do anything with non-matching flags on shl. llvm-svn: 364652
* [InstCombine] remove 'tmp' names and regenerate checks; NFCSanjay Patel2019-06-271-63/+64
| | | | llvm-svn: 364546
* [InstCombine][NFCI] Fix test comments.Huihui Zhang2019-06-272-4/+4
| | | | | | | | | | | | For fold (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0 (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0 Test cases of X being constant are positive tests not negative. Prep work for D62818. llvm-svn: 364497
* [InstCombine] change 'tmp' variable names; NFCSanjay Patel2019-06-261-86/+86
| | | | | | | | | | | I don't think there was anything going wrong here, but the auto-generating CHECK line script is known to have problems with 'TMP' because it uses that to match nameless values. This is a retry of rL364452. llvm-svn: 364477
* Revert [InstCombine] change 'tmp' variable names; NFCSanjay Patel2019-06-261-84/+86
| | | | | | This reverts r364452 (git commit 6083ae0b4a250c69f6d5b13b3742ee1fe5b878d5) llvm-svn: 364455
* [InstCombine] change 'tmp' variable names; NFCSanjay Patel2019-06-261-86/+84
| | | | | | | | | I don't think there was anything going wrong here, but the auto-generating CHECK line script is known to have problems with 'TMP' because it uses that to match nameless values. llvm-svn: 364452
* [InstCombine] regenerate test checks; NFCSanjay Patel2019-06-261-37/+75
| | | | llvm-svn: 364437
* [NFC][InstCombine] Revisit one-use tests in ↵Roman Lebedev2019-06-261-14/+114
| | | | | | shift-amount-reassociation-in-bittest.ll llvm-svn: 364433
* [NFC][InstCombine] Add shift amount reassociation in bittest tests (PR42399)Roman Lebedev2019-06-261-0/+420
| | | | | | | | https://bugs.llvm.org/show_bug.cgi?id=42399 https://rise4fun.com/Alive/kBb https://rise4fun.com/Alive/1SB llvm-svn: 364430
* [NFC][InstCombine] Add shift amount reassociation tests (PR42391)Roman Lebedev2019-06-261-0/+167
| | | | | | | https://bugs.llvm.org/show_bug.cgi?id=42391 https://rise4fun.com/Alive/9E2 llvm-svn: 364393
* [InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 is power of two ↵Huihui Zhang2019-06-252-26/+26
| | | | | | | | | | | | | | | | | | | | | | | -> icmp eq/ne (and %x, (lshr -C1, C2)), 0. Simplify 'shl' inequality test into 'and' equality test. This pattern happens in the middle-end while simplifying bitfield access, Exposed in https://reviews.llvm.org/D63505 https://rise4fun.com/Alive/6uz Reviewers: lebedev.ri, efriedma Reviewed By: lebedev.ri Subscribers: spatel, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63675 llvm-svn: 364348
* [InstCombine] reduce checks for power-of-2-or-zero using ctpopSanjay Patel2019-06-251-47/+28
| | | | | | | | | | | | | | | | | | | | | | | This follows up the transform from rL363956 to use the ctpop intrinsic when checking for power-of-2-or-zero. This is matching the isPowerOf2() patterns used in PR42314: https://bugs.llvm.org/show_bug.cgi?id=42314 But there's at least 1 instcombine follow-up needed to match the alternate form: (v & (v - 1)) == 0; We should have all of the backend expansions handled with: rL364319 (x86-specific changes still needed for optimal code based on subtarget) And the larger patterns to exclude zero as a power-of-2 are joining with this change after: rL364153 ( D63660 ) rL364246 Differential Revision: https://reviews.llvm.org/D63777 llvm-svn: 364341
* [InstCombine][NFC] Add test to show missing fold for icmp ult/uge (shl %x, ↵Huihui Zhang2019-06-251-0/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | C2), C1. Summary: 'shl' inequality test ``` icmp ult/uge (shl %x, C2), C1 iff C1 is power of two ``` can be simplified as 'and' equality test ``` icmp eq/ne (and %x, (lshr -C1, C2)), 0. ``` Reviewers: lebedev.ri, efriedma Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63670 llvm-svn: 364256
* [InstCombine] Fold icmp eq/ne (and %x, C), 0 iff (-C) is power of two -> %x ↵Huihui Zhang2019-06-253-40/+28
| | | | | | | | | | | | | | | | | | | | | | | | | u</u>= (-C) earlier. Summary: To generate simplified IR, make sure fold (X & ~C) ==/!= 0 --> X u</u>= C+1 is scheduled before fold ((X << Y) & C) == 0 -> (X & (C >> Y)) == 0. https://rise4fun.com/Alive/7ZN Reviewers: lebedev.ri, efriedma, spatel, craig.topper Reviewed By: lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63505 llvm-svn: 364255
* [InstCombine] squash is-not-power-of-2 using ctpopSanjay Patel2019-06-241-10/+6
| | | | | | | | | | | | | | | | This is the Demorgan'd 'not' of the pattern handled in: D63660 / rL364153 This is another intermediate IR step towards solving PR42314: https://bugs.llvm.org/show_bug.cgi?id=42314 We can test if a value is not a power-of-2 using ctpop(X) > 1, so combining that with an is-zero check of the input is the same as testing if not exactly 1 bit is set: (X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1 llvm-svn: 364246
* InstCombine: Preserve nuw when reassociating nuw ops [3/3]Matt Arsenault2019-06-241-2/+50
| | | | | | Alive says this is OK. llvm-svn: 364235
* InstCombine: Preserve nuw when reassociating nuw ops [2/3]Matt Arsenault2019-06-241-3/+3
| | | | | | Alive says this is OK. llvm-svn: 364234
* InstCombine: Preserve nuw when reassociating nuw ops [1/3]Matt Arsenault2019-06-241-1/+1
| | | | | | Alive says this is OK. llvm-svn: 364233
* [InstCombine] add tests for more variants of isPowerOf2; NFCSanjay Patel2019-06-241-0/+259
| | | | llvm-svn: 364227
* [InstCombine] Regenerate test pr17827. NFCI.Huihui Zhang2019-06-241-6/+6
| | | | | | Prep work for upcoming patch D63505. llvm-svn: 364224
* [InstCombine] reduce funnel-shift i16 X, X, 8 to bswap XSanjay Patel2019-06-241-3/+9
| | | | | | | | | | Prefer the more exact intrinsic to remove a use of the input value and possibly make further transforms easier (we will still need to match patterns with funnel-shift of wider types as pieces of bswap, especially if we want to canonicalize to funnel-shift with constant shift amount). Discussed in D46760. llvm-svn: 364187
* [InstCombine] add tests for funnel-shift to bswap; NFCSanjay Patel2019-06-241-0/+37
| | | | llvm-svn: 364184
* [InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shiftsSimon Pilgrim2019-06-241-0/+26
| | | | | | | | trunc(lshr) handling - if the shift is out of range (undefined) then bail like we do for non-constant shifts. Fixes OSS Fuzz #15217 llvm-svn: 364181
* [InstCombine] squash is-power-of-2 that uses ctpopSanjay Patel2019-06-231-10/+16
| | | | | | | | | | | | | | | This is another intermediate IR step towards solving PR42314: https://bugs.llvm.org/show_bug.cgi?id=42314 We can test if a value is power-of-2-or-0 using ctpop(X) < 2, so combining that with a non-zero check of the input is the same as testing if exactly 1 bit is set: (X != 0) && (ctpop(X) u< 2) --> ctpop(X) == 1 Differential Revision: https://reviews.llvm.org/D63660 llvm-svn: 364153
* [NFC] Update shl-sub testsDavid Bolvansky2019-06-211-15/+14
| | | | llvm-svn: 364083
* [InstCombine] add tests for ctpop folds; NFCSanjay Patel2019-06-211-0/+117
| | | | llvm-svn: 364082
* [InstCombine] (1 << (C - x)) -> ((1 << C) >> x) if C is bitwidth - 1David Bolvansky2019-06-211-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: ``` %a = sub i32 31, %x %r = shl i32 1, %a => %d = shl i32 1, 31 %r = lshr i32 %d, %x Done: 1 Optimization is correct! ``` https://rise4fun.com/Alive/btZm Reviewers: spatel, lebedev.ri, nikic Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63652 llvm-svn: 364073
* [NFC] Added more tests for D63652David Bolvansky2019-06-211-0/+33
| | | | llvm-svn: 364069
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