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* [InstCombine] Use known overflow information for saturating add/subNikita Popov2018-11-281-18/+14
| | | | | | | | | | | | | If ValueTracking can determine that the add/sub can newer overflow, replace it with the corresponding nuw/nsw add/sub. Additionally, for the unsigned case, if ValueTracking determines that the add/sub always overflows, replace the result with the saturation value. This change is part of https://reviews.llvm.org/D54534. llvm-svn: 347770
* [InstCombine] Canonicalize const arg for saturating addsNikita Popov2018-11-281-6/+6
| | | | | | | | | If a saturating add intrinsic has one constant argument, make sure it is on the RHS. This will simplify further transformations. This change is part of https://reviews.llvm.org/D54534. llvm-svn: 347769
* [InstCombine] Add tests for saturating add/sub; NFCNikita Popov2018-11-271-0/+669
| | | | | | These are baseline tests for D54534. llvm-svn: 347700
* [InstCombine] add tests for rotate/bswap equality; NFCSanjay Patel2018-11-271-0/+23
| | | | llvm-svn: 347618
* [InstCombine] Determine demanded and known bits for funnel shiftsNikita Popov2018-11-241-19/+34
| | | | | | | | | | | | | | Support funnel shifts in InstCombine demanded bits simplification. If the shift amount is constant, we can determine both the demanded bits of the operands, as well as the known bits of the result. If one of the operands has no demanded bits, it will be replaced by undef and the funnel shift will be simplified into a simple shift due to the simplifications added in D54778. Differential Revision: https://reviews.llvm.org/D54869 llvm-svn: 347515
* [InstCombine] Simplify funnel shift with zero/undef operand to shiftNikita Popov2018-11-231-9/+45
| | | | | | | | | | | | | | | | | | | | The following simplifications are implemented: * `fshl(X, 0, C) -> shl X, C%BW` * `fshl(X, undef, C) -> shl X, C%BW` (assuming undef = 0) * `fshl(0, X, C) -> lshr X, BW-C%BW` * `fshl(undef, X, C) -> lshr X, BW-C%BW` (assuming undef = 0) * `fshr(X, 0, C) -> shl X, (BW-C%BW)` * `fshr(X, undef, C) -> shl X, BW-C%BW` (assuming undef = 0) * `fshr(0, X, C) -> lshr X, C%BW` * `fshr(undef, X, C) -> lshr, X, C%BW` (assuming undef = 0) The simplification is only performed if the shift amount C is constant, because we can explicitly compute C%BW and BW-C%BW in this case. Differential Revision: https://reviews.llvm.org/D54778 llvm-svn: 347505
* [InstCombine] Add tests for funnel shift with zero operand; NFCNikita Popov2018-11-211-0/+36
| | | | | | These are additional baseline tests for D54778. llvm-svn: 347414
* [InstCombine] add tests for funnel shifts; NFCSanjay Patel2018-11-201-0/+177
| | | | | | | | These are included in D54666, so adding them first with baseline results. Patch by: @nikic (Nikita Popov) llvm-svn: 347333
* [InstCombine] Set debug loc on `mergeStoreIntoSuccessor` phiVedant Kumar2018-11-191-0/+26
| | | | | | | | | Assigning a merged debug location to the `mergeStoreIntoSuccessor` phi improves backtrace quality. Fixes llvm.org/PR38083. llvm-svn: 347257
* [InstCombine] adjust rotate direction in tests; NFCSanjay Patel2018-11-151-12/+12
| | | | | | Copy/paste errors - all of the changed tests rotated left before. llvm-svn: 346982
* [InstCombine] add tests for funnel shift (rotate) canonicalization; NFCSanjay Patel2018-11-151-1/+342
| | | | llvm-svn: 346975
* [InstCombine] fix rotate narrowing bug for non-pow-2 typesSanjay Patel2018-11-151-16/+16
| | | | llvm-svn: 346968
* [InstCombine] add rotate narrowing tests with odd types; NFCSanjay Patel2018-11-151-0/+46
| | | | | | | | | There's a potential miscompile here. It's unlikely in the real world because this transform is guarded with shouldChangeType(), but this test file doesn't include a standard data-layout for some reason (despite including a custom 1), so we can see the bug. llvm-svn: 346966
* [InstCombine] Remove a couple of asserts based on incorrect assumptionsMandeep Singh Grang2018-11-141-0/+18
| | | | | | | | | | | | | | | | Summary: These asserts are based on the assumption that the order of true/false operands in a select and those in the compare would always be the same. This fixes PR39595. Reviewers: craig.topper, spatel, dmgreen Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54359 llvm-svn: 346874
* [InstCombine] fold funnel shift amount based on demanded bitsSanjay Patel2018-11-131-14/+10
| | | | | | | | | | | | | | The shift amount of a funnel shift is modulo the scalar bitwidth: http://llvm.org/docs/LangRef.html#llvm-fshl-intrinsic ...so we can use demanded bits analysis on that operand to simplify it when we have a power-of-2 bitwidth. This is another step towards canonicalizing {shift/shift/or} to the intrinsics in IR. Differential Revision: https://reviews.llvm.org/D54478 llvm-svn: 346814
* [InstCombine] canonicalize rotate patterns with cmp/selectSanjay Patel2018-11-131-37/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cmp+branch variant of this pattern is shown in: https://bugs.llvm.org/show_bug.cgi?id=34924 ...and as discussed there, we probably can't transform that without a rotate intrinsic. We do have that now via funnel shift, but we're not quite ready to canonicalize IR to that form yet. The case with 'select' should already be transformed though, so that's this patch. The sequence with negation followed by masking is what we use in the backend and partly in clang (though that part should be updated). https://rise4fun.com/Alive/TplC %cmp = icmp eq i32 %shamt, 0 %sub = sub i32 32, %shamt %shr = lshr i32 %x, %shamt %shl = shl i32 %x, %sub %or = or i32 %shr, %shl %r = select i1 %cmp, i32 %x, i32 %or => %neg = sub i32 0, %shamt %masked = and i32 %shamt, 31 %maskedneg = and i32 %neg, 31 %shl2 = lshr i32 %x, %masked %shr2 = shl i32 %x, %maskedneg %r = or i32 %shl2, %shr2 llvm-svn: 346807
* [InstCombine] add tests for funnel shift demanded bits; NFCSanjay Patel2018-11-131-0/+147
| | | | llvm-svn: 346762
* [InstCombine] add rotate variants that include select; NFCSanjay Patel2018-11-121-0/+84
| | | | llvm-svn: 346719
* [InstCombine] narrow width of rotate patterns, part 3Sanjay Patel2018-11-121-44/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a longer variant for the pattern handled in rL346713 This one includes zexts. Eventually, we should canonicalize all rotate patterns to the funnel shift intrinsics, but we need a bit more infrastructure to make sure the vectorizers handle those intrinsics as well as the shift+logic ops. https://rise4fun.com/Alive/FMn Name: narrow rotateright %neg = sub i8 0, %shamt %rshamt = and i8 %shamt, 7 %rshamtconv = zext i8 %rshamt to i32 %lshamt = and i8 %neg, 7 %lshamtconv = zext i8 %lshamt to i32 %conv = zext i8 %x to i32 %shr = lshr i32 %conv, %rshamtconv %shl = shl i32 %conv, %lshamtconv %or = or i32 %shl, %shr %r = trunc i32 %or to i8 => %maskedShAmt2 = and i8 %shamt, 7 %negShAmt2 = sub i8 0, %shamt %maskedNegShAmt2 = and i8 %negShAmt2, 7 %shl2 = lshr i8 %x, %maskedShAmt2 %shr2 = shl i8 %x, %maskedNegShAmt2 %r = or i8 %shl2, %shr2 llvm-svn: 346716
* [InstCombine] narrow width of rotate patterns, part 2 (PR39624)Sanjay Patel2018-11-121-32/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sub-pattern for the shift amount in a rotate can take on several different forms, and there's apparently no way to canonicalize those without seeing the entire rotate sequence. This is the form noted in: https://bugs.llvm.org/show_bug.cgi?id=39624 https://rise4fun.com/Alive/qnT %zx = zext i8 %x to i32 %maskedShAmt = and i32 %shAmt, 7 %shl = shl i32 %zx, %maskedShAmt %negShAmt = sub i32 0, %shAmt %maskedNegShAmt = and i32 %negShAmt, 7 %shr = lshr i32 %zx, %maskedNegShAmt %rot = or i32 %shl, %shr %r = trunc i32 %rot to i8 => %truncShAmt = trunc i32 %shAmt to i8 %maskedShAmt2 = and i8 %truncShAmt, 7 %shl2 = shl i8 %x, %maskedShAmt2 %negShAmt2 = sub i8 0, %truncShAmt %maskedNegShAmt2 = and i8 %negShAmt2, 7 %shr2 = lshr i8 %x, %maskedNegShAmt2 %r = or i8 %shl2, %shr2 llvm-svn: 346713
* [InstCombine] add more tests for rotate narrowing; NFCSanjay Patel2018-11-121-43/+144
| | | | llvm-svn: 346703
* [InstCombine] regenerate checks; NFCSanjay Patel2018-11-121-15/+16
| | | | llvm-svn: 346689
* [InstCombine] auto-generate full checks; NFCSanjay Patel2018-11-102-206/+304
| | | | llvm-svn: 346594
* InstCombine: Avoid introducing poison values when lowering llvm.amdgcn.[us]bfeTom Stellard2018-11-081-23/+7
| | | | | | | | | | | | | | | | | | | Summary: When the 3rd argument to these intrinsics is zero, lowering them to shift instructions produces poison values, since we end up with shift amounts equal to the number of bits in the shifted value. This means we can only lower these intrinsics if we can prove that the 3rd argument is not zero. Reviewers: arsenm Reviewed By: arsenm Subscribers: bnieuwenhuizen, jvesely, wdng, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D53739 llvm-svn: 346422
* [InstCombine] propagate FMF for fcmp+fabs foldsSanjay Patel2018-11-071-12/+12
| | | | | | | By morphing the instruction rather than deleting and creating a new one, we retain fast-math-flags and potentially other metadata (profile info?). llvm-svn: 346331
* [InstCombine] peek through fabs() when checking isnan()Sanjay Patel2018-11-071-4/+2
| | | | | | | | | That should be the end of the missing cases for this fold. See earlier patches in this series: rL346321 rL346324 llvm-svn: 346327
* [InstCombine] add tests for isnan(fabs(X)); NFCSanjay Patel2018-11-071-0/+22
| | | | llvm-svn: 346325
* [InstCombine] add folds for fcmp Pred fabs(X), 0.0Sanjay Patel2018-11-071-4/+2
| | | | | | | | Similar to rL346321, we had folds for the ordered versions of these compares already, so add the unordered siblings for completeness. llvm-svn: 346324
* [InstCombine] add tests for more fcmp+fabs preds; NFCSanjay Patel2018-11-071-0/+22
| | | | llvm-svn: 346323
* [InstCombine] add fold for fabs(X) u< 0.0Sanjay Patel2018-11-071-2/+1
| | | | | | | | | | | | | | The sibling fold for 'oge' --> 'ord' was already here, but this half was missing. The result of fabs() must be positive or nan, so asking if the result is negative or nan is the same as asking if the result is nan. This is another step towards fixing: https://bugs.llvm.org/show_bug.cgi?id=39475 llvm-svn: 346321
* [InstCombine] add test for fcmp+fabs; NFCSanjay Patel2018-11-071-0/+20
| | | | llvm-svn: 346320
* [InstCombine] add FMF to fcmp to show failure to propagate; NFCSanjay Patel2018-11-071-7/+7
| | | | llvm-svn: 346317
* [InstCombine] do not shrink switch conditions to illegal types (PR29009)Sanjay Patel2018-11-071-7/+61
| | | | | | | | | | | | | | | | | This patch makes shrinking switch conditions less aggressive which was introduced by: rL274233 Note that we have 2 new bugs to track potential follow-ups that might have solved PR29009 in different ways: https://bugs.llvm.org/show_bug.cgi?id=39569 https://bugs.llvm.org/show_bug.cgi?id=39578 Patch by: @dendibakh (Denis Bakhvalov) Differential Revision: https://reviews.llvm.org/D54115 llvm-svn: 346315
* [InstCombine] allow vector types for fcmp+fpext foldSanjay Patel2018-11-061-2/+1
| | | | llvm-svn: 346245
* [InstCombine] add vector test for fcmp+fpext; NFCSanjay Patel2018-11-061-8/+19
| | | | llvm-svn: 346243
* [InstCombine] propagate fast-math-flags when folding fcmp+fpext, part 2Sanjay Patel2018-11-061-1/+1
| | | | llvm-svn: 346242
* [InstCombine] propagate fast-math-flags when folding fcmp+fpextSanjay Patel2018-11-061-1/+1
| | | | llvm-svn: 346240
* [InstCombine] adjust tests to show dropping FMF; NFCSanjay Patel2018-11-061-2/+2
| | | | llvm-svn: 346239
* [InstCombine] propagate fast-math-flags when folding fcmp+fneg, part 2Sanjay Patel2018-11-061-2/+2
| | | | llvm-svn: 346238
* [InstCombine] adjust tests to show dropping FMF; NFCSanjay Patel2018-11-061-4/+4
| | | | | | Also, remove some stale FIXME comments ( rL346234 ). llvm-svn: 346236
* [InstCombine] propagate fast-math-flags when folding fcmp+fnegSanjay Patel2018-11-061-2/+2
| | | | | | | | | | This is another part of solving PR39475: https://bugs.llvm.org/show_bug.cgi?id=39475 This might be enough to fix that particular issue, but as noted with the FIXME, we're still dropping FMF on other folds around here. llvm-svn: 346234
* [InstCombine] add tests for FMF propagation failure; NFCSanjay Patel2018-11-061-0/+24
| | | | llvm-svn: 346232
* [InstCombine] Ensure nested shifts are in range (OSS-Fuzz #9880)Simon Pilgrim2018-11-061-0/+19
| | | | llvm-svn: 346225
* [InstCombine] add/adjust tests for fcmp+select substitution; NFCSanjay Patel2018-11-051-28/+91
| | | | | | | | There was no coverage for at least 2 out of the 4 patterns because of fcmp canonicalization. The tests and code should be moved to InstSimplify in a follow-up because this doesn't create any new values. llvm-svn: 346150
* [InstCombine] canonicalize -0.0 to +0.0 in fcmpSanjay Patel2018-11-054-25/+25
| | | | | | | | | | | | | | | | | As stated in IEEE-754 and discussed in: https://bugs.llvm.org/show_bug.cgi?id=38086 ...the sign of zero does not affect any FP compare predicate. Known regressions were fixed with: rL346097 (D54001) rL346143 The transform will help reduce pattern-matching complexity to solve: https://bugs.llvm.org/show_bug.cgi?id=39475 ...as well as improve CSE and codegen (a zero constant is almost always easier to produce than 0x80..00). llvm-svn: 346147
* [InstCombine] loosen FP 0.0 constraint for fcmp+select substitutionSanjay Patel2018-11-051-21/+14
| | | | | | | | | | | | | | It looks like we correctly removed edge cases with 0.0 from D50714, but we were a bit conservative because getBinOpIdentity() doesn't distinguish between +0.0 and -0.0 and 'nsz' is effectively always true for fcmp (see discussion in: https://bugs.llvm.org/show_bug.cgi?id=38086 Without this change, we would get regressions by canonicalizing to +0.0 in all fcmp, and that's a step towards solving: https://bugs.llvm.org/show_bug.cgi?id=39475 llvm-svn: 346143
* [InstCombine] adjust tests for select with FP identity op; NFCSanjay Patel2018-11-051-30/+32
| | | | | | These are mislabeled as negative tests. llvm-svn: 346142
* [InstCombine] add/adjust tests for select with fsub identity op; NFCSanjay Patel2018-11-051-4/+22
| | | | llvm-svn: 346138
* [InstCombine] add tests for select with FP identity op; NFCSanjay Patel2018-11-051-0/+64
| | | | llvm-svn: 346136
* [ValueTracking] determine sign of 0.0 from select when matching min/max FPSanjay Patel2018-11-041-23/+15
| | | | | | | | | | | | | | | | | | | In PR39475: https://bugs.llvm.org/show_bug.cgi?id=39475 ..we may fail to recognize/simplify fabs() in some cases because we do not canonicalize fcmp with a -0.0 operand. Adding that canonicalization can cause regressions on min/max FP tests, so that's this patch: for the purpose of determining whether something is min/max, let the value returned by the select determine how we treat a 0.0 operand in the fcmp. This patch doesn't actually change the -0.0 to +0.0. It just changes the analysis, so we don't fail to recognize equivalent min/max patterns that only differ in the signbit of 0.0. Differential Revision: https://reviews.llvm.org/D54001 llvm-svn: 346097
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