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* [globalisel][tablegen] Add support for multi-insn emissionDaniel Sanders2017-11-011-8/+15
| | | | | | | | | | | | | | The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-1/+1
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-161-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-23/+9
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-9/+23
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-141-38/+62
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-131-8/+74
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [TableGen] Allow intrinsics to have up to 8 return values.Artem Belevich2017-10-121-0/+32
| | | | | | Differential Revision: https://reviews.llvm.org/D38633 llvm-svn: 315598
* [globalisel] Add support for ValueType operands in patterns.Daniel Sanders2017-10-091-32/+53
| | | | | | | | | | | | It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-142-19/+46
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* Address r311914 review commentsMatthias Braun2017-08-281-0/+6
| | | | llvm-svn: 311917
* TableGen: Fix subreg composition/concatenationMatthias Braun2017-08-281-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes 2 problems in subregister hierarchies with multiple levels and tuples: 1) For bigger tuples computing secondary subregs would miss 2nd order effects. In the test case a register like `S10_S11_S12_S13_S14` with D5 = S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5, sub1 = D6 but would miss the fact that we could now form ssub0_ssub1_ssub2_ssub3 (aka sub0_sub1) = D5_D6. This is fixed by changing computeSecondarySubRegs() to compute a fixpoint. 2) Fixing 1) exposed a problem where TableGen would create multiple names for effectively the same subregister index. In the test case the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is composed from ssub2 and ssub3. TableGen should not create both sub0_sub1 and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes the code to build a transitive closure of the subregister components before forming new concatenated subregister indexes. This fix was developed for an out of tree target. For the in-tree targets the only change is in the register information computed for ARM. There is a slight chance this fixed/improved some register coalescing around the QQQQ/QQ register classes there but I couldn't see/provoke any code generation differences. Differential Revision: https://reviews.llvm.org/D36913 llvm-svn: 311914
* [globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not ↵Daniel Sanders2017-08-241-1/+2
| | | | | | | | | GIPFP_Invalid This fixes a warning when there are zero defined predicates and also fixes an unnoticed bug where the first predicate in the table was unusable. llvm-svn: 311684
* Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-241-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
* Revert r311546 as it breaks buildVictor Leschuk2017-08-231-38/+6
| | | | | | http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4394 llvm-svn: 311560
* [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-231-6/+38
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311546
* [globalisel][tablegen] Add tests for FeatureBitsets and ComplexPattern ↵Daniel Sanders2017-08-231-1/+20
| | | | | | predicates. llvm-svn: 311542
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-171-0/+7
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 311084
* Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-151-7/+0
| | | | | | | | | | As expected, this failed on the windows bots but the instrumentation showed something interesting. The ADD8ri and INC8r rules are never directly compared on the windows machines. That implies that the issue lies in transitivity of the Compare predicate. I believe I've already verified that but maybe I missed something. llvm-svn: 310922
* Re-commit with some instrumentation: [globalisel][tablegen] Support ↵Daniel Sanders2017-08-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on the windows bots and this one is likely to fail on those same bots. However, the added instrumentation should reveal a particular isHigherPriorityThan() evaluation which I'm expecting to expose that these machines are weighing priority of two rules differently from the non-windows machines. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310919
* Revert r310716 (and r310735): [globalisel][tablegen] Support ↵Daniel Sanders2017-08-111-7/+0
| | | | | | | | | | | zero-instruction emission. Two of the Windows bots are failing test\CodeGen\X86\GlobalISel\select-inc.mir which should not have been affected by the change. Reverting while I investigate. Also reverted r310735 because it builds on r310716. llvm-svn: 310745
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-111-0/+7
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 310735
* [globalisel][tablegen] Add support for importing 'imm' operands.Daniel Sanders2017-08-081-7/+30
| | | | | | | | | | | | | | | | | | | Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
* [GlobalISel] Only merge memory ops for mayLoad or mayStore instrs.Florian Hahn2017-08-031-16/+4
| | | | | | | | | | | | | | | | Summary: We only need to merge memory operands for instructions that access memory. This slightly reduces the number of actions executed. Reviewers: MatzeB, rovka, dsanders Reviewed By: dsanders Subscribers: aemerson, igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36151 llvm-svn: 309944
* [globalisel][tablegen] Do not merge memoperands from instructions that ↵Daniel Sanders2017-08-021-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | weren't in the match. Summary: Fix a bug discovered in an out-of-tree target where memoperands from pseudo-instructions that weren't part of the match were being merged into the result instructions as part of GIR_MergeMemOperands. This bug was caused by a change to the handling of State.MIs between rules when the state machine tables were fused into a single table. Previously, each rule would reset State.MIs using State.MIs.resize(1) but this is no longer done, as a result stale data is occasionally left in some elements of State.MIs. Most opcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands from the intructions recorded in State.MIs into the result instruction. Suppose for example, we processed but rejected the following pattern: (signextend (load x)) at this point, State.MIs contains the signextend and the load. Now suppose we process and accept this pattern: (add x, y) at this point, State.MIs contains the add as well as the (now irrelevant) load. When GIR_MergeMemOperands is processed, the memoperands from that irrelevant load will be merged into the result instruction even though it was not part of the match. Bringing back the State.MIs.resize(1) would fix the problem but it would limit our ability to optimize the table in the future. Instead, this patch fixes the problem by explicitly stating which instructions should be merged into the result. There's no direct test case in this commit because a test case would be very brittle. However, at the time of writing this should fix the failures in http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/ as well as a failure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: fhahn, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36094 llvm-svn: 309804
* Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-271-165/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). The compile-time regressions from the last commit were caused by the ARM target including a non-const variable (zero_reg) in the table and therefore generating an initializer for it. That variable is now const. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309264
* Revert r309094: [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-35/+165
| | | | | | | | The ARM bots have started failing and while this patch should be an improvement for these bots, it's also the only suspect in the blamelist. Reverting while Diana and I investigate the problem. llvm-svn: 309111
* [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-165/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309094
* [globalisel][tablegen] Add control-flow to the MatchTable.Daniel Sanders2017-07-201-4/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This will allow us to merge the various sub-tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. The bulk of this patch is a mechanical conversion to the new MatchTable object which is responsible for tracking label definitions and filling in the index of the jump targets. It is also responsible for nicely formatting the table. This was necessary to support the new GIM_Try opcode which takes the index to jump to if the match should fail. This value is unknown during table construction and is filled in during emission. To support nesting try-blocks (although we currently don't emit tables with nested try-blocks), GIM_Reject has been re-introduced to explicitly exit a try-block or fail the overall match if there are no active try-blocks. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35117 llvm-svn: 308596
* Make shell redirection construct portableKamil Rytarowski2017-07-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: NetBSD shell sh(1) does not support ">& /dev/null" construct. This is bashism. The portable and POSIX solution is to use: "> /dev/null 2>&1". This change fixes 22 Unexpected Failures on NetBSD/amd64 for the "check-llvm" target. Sponsored by <The NetBSD Foundation> Reviewers: joerg, dim, rnk Reviewed By: joerg, rnk Subscribers: rnk, davide, llvm-commits Differential Revision: https://reviews.llvm.org/D35277 llvm-svn: 307789
* [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is ↵Daniel Sanders2017-07-111-46/+102
| | | | | | | | | | | | | | | | | | | | | | used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-111-2/+2
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. ↵Craig Topper2017-07-071-0/+1
| | | | | | This is required after r307358. llvm-svn: 307361
* [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-07-061-39/+76
| | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
* [globalisel][tablegen] Finish fixing compile-time regressions by merging the ↵Daniel Sanders2017-07-051-273/+167
| | | | | | | | | | | | | | | | | | | | | | | matcher and emitter state machines. Summary: Also, made a few minor tweaks to shave off a little more cumulative memory consumption: * All rules share a single NewMIs instead of constructing their own. Only one will end up using it. * Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent GIM_RecordInsn from changing MIs[0]. Depends on D33764 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33766 llvm-svn: 307159
* [globalisel][tablegen] Added instruction emission to the state-machine-based ↵Daniel Sanders2017-07-051-155/+221
| | | | | | | | | | | | | | | | | | | | | | | matcher. Summary: This further improves the compile-time regressions that will be caused by a re-commit of r303259. Also added included preliminary work in preparation for the multi-insn emitter since I needed to change the relevant part of the API for this patch anyway. Depends on D33758 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33764 llvm-svn: 307133
* [globalisel][tablegen] Partially fix compile-time regressions by converting ↵Daniel Sanders2017-07-041-363/+495
| | | | | | | | | | | | | | | | | | | | | | matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
* [globalisel][tablegen] Add support for COPY_TO_REGCLASS.Daniel Sanders2017-06-201-0/+26
| | | | | | | | | | | | | | | | | | | | | | Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
* [globalisel][tablegen] Add support for (set $dst, 1) and test X86's ↵Daniel Sanders2017-05-231-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
* Revert r303259 - [globalisel][tablegen] Import rules containing ↵Daniel Sanders2017-05-221-35/+0
| | | | | | | | | | | intrinsic_wo_chain. It's causing some buildbots to timeout whenever tablegen needs re-compilation, particularly those with -fsanitize=memory but not only them. A compile time regression was expected since it triples the amount of SelectionDAG rules we are able to import but it's currently too high. llvm-svn: 303542
* [MVT] add v1i1 MVTGuy Blank2017-05-181-1/+1
| | | | | | | | Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
* Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-181-0/+35
| | | | | | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 The previous commit failed on test-suite/Bitcode/simd_ops/AArch64_halide_runtime.bc because isImmOperandEqual() assumed MO was a register operand and that's not always true. llvm-svn: 303341
* Revert "[globalisel][tablegen] Import rules containing intrinsic_wo_chain."Quentin Colombet2017-05-171-35/+0
| | | | | | | | | This reverts commit r303259. This breaks the GISel bot: http://lab.llvm.org:8080/green/job/Compiler_Verifiers_GlobalISEL/5163/consoleFull#-134276167849ba4694-19c4-4d7e-bec5-911270d8a58c llvm-svn: 303313
* [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-05-171-0/+35
| | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 303259
* [globalisel][tablegen] Require that all registers between instructions of a ↵Daniel Sanders2017-05-171-0/+4
| | | | | | | | | | | | | | | | | | | match are virtual. Summary: Without this, it's possible to encounter multiple defs for a register. This is triggered by the current version of D32868 when applied to trunk. Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls Reviewed By: qcolombet Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32869 llvm-svn: 303253
* [GlobalISel][TableGen] Fix handling of default operandsDiana Picus2017-05-171-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
* [TableGen] Add EncoderMethod to RegisterOperandSam Kolton2017-05-152-1/+36
| | | | | | | | Reviewers: stoklund, grosbach, vpykhtin Differential Revision: https://reviews.llvm.org/D32493 llvm-svn: 303044
* [globalisel][tablegen] Fix the test after silencing the unused variable ↵Daniel Sanders2017-04-291-7/+0
| | | | | | warning in r301755. llvm-svn: 301756
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