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* [MS][ARM64] Hoist __ImageBase handling into TargetLoweringObjectFileCOFFReid Kleckner2018-06-121-0/+11
| | | | | | | | | | | | All COFF targets should use @IMGREL32 relocations for symbol differences against __ImageBase. Do the same for getSectionForConstant, so that immediates lowered to globals get merged across TUs. Patch by Chris January Differential Revision: https://reviews.llvm.org/D47783 llvm-svn: 334523
* [MC] [X86] Teach leaq _GLOBAL_OFFSET_TABLE(%rip), %r15 to use ↵Fangrui Song2018-06-121-13/+17
| | | | | | | | | | | | | | | | | | | R_X86_64_GOTPC32 instead of R_X86_64_PC32 Summary: This is similar to D46319 (ARM). x86-64 psABI p40 gives an example: leaq _GLOBAL_OFFSET_TABLE(%rip), %r15 # GOTPC32 reloc GNU as creates R_X86_64_GOTPC32. However, MC currently emits R_X86_64_PC32. Reviewers: javed.absar, echristo Subscribers: kristof.beyls, llvm-commits, peter.smith, grimar Differential Revision: https://reviews.llvm.org/D47507 llvm-svn: 334515
* [DWARFv5] llvm-mc -dwarf-version does not imply -g.Paul Robinson2018-06-124-24/+19
| | | | | | | | | | | | | Don't provide the assembler source as the "root file" unless the user asked to have debug info for the assembler source (with -g). If the source doesn't provide an explicit ".file 0" then (a) use the compilation directory as directory #0, and (b) use the file #1 info for file #0 also. Differential Revision: https://reviews.llvm.org/D48055 llvm-svn: 334512
* [mips] Guard some floating point instructions correctlySimon Dardis2018-06-122-1/+35
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47636 llvm-svn: 334491
* AMDGPU: Add 64-bit relative variant kindKonstantin Zhuravlyov2018-06-111-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D47601 llvm-svn: 334443
* [X86] Add encoding tests for avx5124fmaps and avx5124vnni instructions.Craig Topper2018-06-112-0/+91
| | | | | | I forgot to git add these in r333812 llvm-svn: 334387
* [Sparc] Add support for 13-bit PICDaniel Cederman2018-06-112-0/+28
| | | | | | | | | | | | | | | | | Summary: When compiling with -fpic, in contrast to -fPIC, use only the immediate field to index into the GOT. This saves space if the GOT is known to be small. The linker will warn if the GOT is too large for this method. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: brad, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47136 llvm-svn: 334383
* [RISCV] Implement MC layer support for the fence.tso instructionAlex Bradbury2018-06-082-0/+6
| | | | | | | | | | | The instruction makes use of a previously ignored field in the fence instruction. It is introduced in the version 2.3 draft of the RISC-V specification after much work by the Memory Model Task Group. As clarified here <https://github.com/riscv/riscv-isa-manual/issues/186>, the fence.tso assembler mnemonic does not have operands. llvm-svn: 334278
* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-077-17/+346
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler. This patch supersedes D41949. Differential Revision: https://reviews.llvm.org/D46118 Patch by Mario Werner. llvm-svn: 334203
* [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 ↵Craig Topper2018-06-061-0/+3
| | | | | | | | | | are used as the index. These encodings correspond to the cases in the normal encoding scheme where there is no index and our modrm reading code initially decodes it as such. The VSIB handling code tried to compensate for this, but failed to add the base needed to make later code do the right thing. Fixes PR37712. llvm-svn: 334121
* Fix the test case that places intermediate in source directory.Han Shen2018-06-061-1/+1
| | | | | | | | This causes "permission denied" error in some controlled test environment where source tree is read-only. Differential Revision: https://reviews.llvm.org/D47839 llvm-svn: 334114
* [mips] Partially revert r334031Simon Dardis2018-06-061-19/+0
| | | | | | | | The test changes in r334031 give unstable pass/fail results on the llvm-clang-x86_64-expensive-checks-win buildbot. Revert the test changes to turn the bot green. llvm-svn: 334084
* [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixupPeter Smith2018-06-064-0/+85
| | | | | | | | | | | | | | | | | | On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
* [mips] Fix the predicates for arithmetic operationsSimon Dardis2018-06-051-0/+19
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47635 llvm-svn: 334031
* [MC][X86] Allow assembler variable assignment to register name.Nirav Dave2018-06-051-0/+16
| | | | | | | | | | | | | | | | | | | Summary: Allow extended parsing of variable assembler assignment syntax and modify X86 to permit VAR = register assignment. As we emit these as .set directives when possible, we inline such expressions in output assembly. Fixes PR37425. Reviewers: rnk, void, echristo Reviewed By: rnk Subscribers: nickdesaulniers, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D47545 llvm-svn: 334022
* [MC][ARM] Add range checking for Thumb2 resolved fixups.Peter Smith2018-06-051-0/+96
| | | | | | | | | | | | When the branch target of a Thumb2 unconditional or conditonal branch is resolved at assembly time, no range checking is performed on the result leading to incorrect immediates. This change adds a range check: +- 16 Megabytes for unconditional branches, +- 1 Megabyte for the conditional branch. Differential Revision: https://reviews.llvm.org/D46306 llvm-svn: 333997
* [MC][ARM] Correct Thumb BL instruction rangePeter Smith2018-06-051-12/+40
| | | | | | | | | | | | The Thumb BL range is + or - either 16 Megabytes or 4 Megabytes depending on whether the CPU supports Thumb2 or the v8-m baseline ops. The existing check for BL range is incorrectly set at +- 32 Megabytes. This change corrects the higher range and uses the lower range if the featurebits don't have the necessary support for it. Differential Revision: https://reviews.llvm.org/D46305 llvm-svn: 333991
* [AArch64][SVE] Fix range for DUP immediates (16bit elts)Sander de Smalen2018-06-044-46/+53
| | | | | | | | | | | | | | | For immediates used in DUP instructions that have the range -128 to 127, or a multiple of 256 in the range -32768 to 32512, one could argue that when the result element size is 16bits (.h), the value can be considered both signed and unsigned. Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47619 llvm-svn: 333873
* [AArch64][SVE] Asm: Print indexed element 0 as FPR.Sander de Smalen2018-06-043-10/+65
| | | | | | | | | | | | | | | | | | | | Print the first indexed element as a FP register, for example: mov z0.d, z1.d[0] Is now printed as: mov z0.d, d1 Next to printing, this patch also adds aliases to parse 'mov z0.d, d1'. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47571 llvm-svn: 333872
* [AArch64][SVE] Asm: Support for indexed DUP instructions.Sander de Smalen2018-06-044-3/+234
| | | | | | | | | | | | | | | | | | | | Unpredicated copy of indexed SVE element to SVE vector, along with MOV-aliases. For example: dup z0.h, z1.h[0] duplicates the first 16-bit element from z1 to all elements in the result vector z0. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47570 llvm-svn: 333871
* [AArch64][SVE] Asm: Support for FCPY immediate instructions.Sander de Smalen2018-06-044-0/+3265
| | | | | | | | | | | | | Predicated copy of floating-point immediate value to SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: javed.absar Differential Revision: https://reviews.llvm.org/D47518 llvm-svn: 333869
* [AArch64][SVE] Asm: Support for CPY immediate instructionsSander de Smalen2018-06-044-0/+588
| | | | | | | | | | | | | Predicated copy of possibly shifted immediate value into SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47517 llvm-svn: 333868
* [MC] Add assembler support for .cg_profile.Michael J. Spencer2018-06-023-0/+116
| | | | | | | | | | | | | | | Object FIle Representation At codegen time this is emitted into the ELF file a pair of symbol indices and a weight. In assembly it looks like: .cg_profile a, b, 32 .cg_profile freq, a, 11 .cg_profile freq, b, 20 When writing an ELF file these are put into a SHT_LLVM_CALL_GRAPH_PROFILE (0x6fff4c02) section as (uint32_t, uint32_t, uint64_t) tuples as (from symbol index, to symbol index, weight). Differential Revision: https://reviews.llvm.org/D44965 llvm-svn: 333823
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-014-27/+175
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Extend list of relocations supported by the `.reloc` directiveSimon Atanasyan2018-06-011-12/+173
| | | | | | | Supporting GOT and TLS related relocations by the `.reloc` directive is useful for purpose of testing various tools like a linker, for example. llvm-svn: 333773
* [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.Sander de Smalen2018-06-014-0/+1734
| | | | | | | | | | | | | Unpredicated copy of floating-point immediate value into SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47482 llvm-svn: 333744
* [mips] Guard 'nop' properly and add mips16's nop instructionSimon Dardis2018-06-012-0/+13
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47583 llvm-svn: 333739
* [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.Sander de Smalen2018-06-014-24/+167
| | | | | | | | | | | | | Unpredicated copy of repeating immediate pattern to SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47328 llvm-svn: 333731
* [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg ↵Craig Topper2018-06-011-0/+4
| | | | | | | | encodes a GPR. This is different than the behavior of EVEX.X extending modrm.rm to 5 bits. llvm-svn: 333728
* [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when ↵Craig Topper2018-06-011-0/+5
| | | | | | modrm.rm encodes a k-register. llvm-svn: 333727
* Implemented sane default for llvm-objdump's relocation Value formatDaniel Cederman2018-06-012-7/+7
| | | | | | | | | | | | | | | | | | | | | Summary: "Unknown" for platforms that were not manually added into the switch did not make sense at all. Now it prints Target + addend for all elf-machines that were not explicitly mentioned. Addresses PR21059 and PR25124. Original author: fedor.sergeev Reviewers: jyknight, espindola, fedor.sergeev Reviewed By: jyknight Subscribers: eraman, dcederman, jfb, dschuff, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D36464 llvm-svn: 333726
* [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.Craig Topper2018-06-011-1/+1
| | | | | | A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. llvm-svn: 333725
* [X86] Add a test case showing a bad disassembling of an EVEX instruction ↵Craig Topper2018-06-011-0/+3
| | | | | | | | with EVEX.X=0 and a GPR encoded in modrm.rm. EVEX.X is used to extended modrm.rm when the instruction encodes a XMM/YMM/ZMM register. But we aren't properly ignoring it when it encodes a GPR and we end up printing whatever registers exist in X86 register enum after the GPRs. llvm-svn: 333724
* [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of ↵Craig Topper2018-06-011-0/+4
| | | | | | | | | | memory operations. This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3. I think there are still more bugs related to this. llvm-svn: 333722
* [X86] Make sure the check for VEX.vvvv being all ones on instructions that ↵Craig Topper2018-06-011-0/+4
| | | | | | don't use it doesn't ignore a bit in 32-bit mode. llvm-svn: 333717
* [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.Craig Topper2018-06-011-2/+2
| | | | llvm-svn: 333714
* [X86] Add test cases showing the disassembler producing an xmm16-xmm31 ↵Craig Topper2018-06-011-0/+6
| | | | | | | | register in 32-bit mode. We aren't properly suppressing the reading of VEX.R' and VEX.V' in 32-bit mode. llvm-svn: 333713
* [MC] Fallback on DWARF when generating compact unwind on AArch64Francis Visoiu Mistrih2018-05-311-0/+15
| | | | | | | | | | | | | | | Instead of asserting when using the def_cfa directive with a register different from fp, fallback on DWARF. Easily triggered with: .cfi_def_cfa x1, 32; rdar://40249694 Differential Revision: https://reviews.llvm.org/D47593 llvm-svn: 333667
* [mips] Guard all short instructions correctly.Simon Dardis2018-05-313-11/+70
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
* [mips] Correct the predicates of arithmetic and logic instructions.Simon Dardis2018-05-305-5/+14
| | | | | | | | | | | | As part of this effort, duplicate and correct the predicates of some aliases. Also disable code generation of some short form instructions for FastISel, as it would otherwise reject them. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47075 llvm-svn: 333530
* AArch64: print correct annotation for ADRP addresses.Tim Northover2018-05-301-0/+9
| | | | | | | The immediate on an ADRP MCInst needs to be multiplied by 0x1000 to obtain the actual PC-offset that will be calculated. llvm-svn: 333525
* [AArch64][AsmParser] Fix segfault on illegal fpimm.Sander de Smalen2018-05-301-0/+5
| | | | | | | | | | | | | Floating point immediate combining a negative sign and a hexadecimal number, e.g. #-0x0 caused the compiler to crash. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: javed.absar Differential Revision: https://reviews.llvm.org/D47483 llvm-svn: 333524
* [WebAssembly] MC: Add compile-twice test and fix corresponding bugSam Clegg2018-05-301-0/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D47398 llvm-svn: 333494
* [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo tableShiva Chen2018-05-303-7/+29
| | | | | | | | | | | | Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
* [mips] Process numeric register name in the .set assignment directiveSimon Atanasyan2018-05-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Now LLVM assembler cannot process the following code and generates an error. GNU tools support .set assignment directive with numeric register name. ``` .set r4, 4 test.s:1:11: error: invalid token in expression .set r4, $4 ^ ``` This patch teach assembler to handle such directives correctly. Unfortunately a numeric register name cannot be represented as an expression. That's why we have to maintain a separate `StringMap` in the `MipsAsmParser` to keep mapping between aliases names and register numbers. Differential revision: https://reviews.llvm.org/D47464 llvm-svn: 333428
* [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)Sander de Smalen2018-05-294-0/+84
| | | | | | | | | | Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47365 llvm-svn: 333422
* [CodeView] Add prefix to CodeView registers.Jonas Devlieghere2018-05-291-4/+4
| | | | | | | | | | | | | Adds CVReg to CodeView register names to prevent a duplicate symbol with CR3 defined in termios.h, as suggested by Zachary on the mailing list. http://lists.llvm.org/pipermail/llvm-dev/2018-May/123372.html Differential revision: https://reviews.llvm.org/D47478 rdar://39863705 llvm-svn: 333421
* [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.Sander de Smalen2018-05-2914-24/+800
| | | | | | | | | | | | | | | | | | | | | This patch addresses the following variants: - bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'. - unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'. - predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'. And also several aliases, such as: - ORN, alias of ORR. - EON, alias of EOR. - BIC, alias of AND (immediate variant) - MOV, alias of ORR (if unpredicated and source register operands are the same) Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47363 llvm-svn: 333414
* [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 ↵Simon Atanasyan2018-05-291-1/+33
| | | | | | | | | | | | | relocations Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel())) expressions in case of microMIPS. Differential Revision: http://reviews.llvm.org/D47220 llvm-svn: 333409
* [AArch64][SVE] Asm: Support for ADD (immediate) instructions.Sander de Smalen2018-05-296-2/+323
| | | | | | | | | | | | | | | | | | | This patch adds addsub_imm8_opt_lsl_(i8|i16|i32|i64) operands that are unsigned values in the range 0 to 255. For element widths of 16 bits or higher it may also be a signed multiple of 256 in the range 0 to 65280. Note: This also does some refactoring to reuse convenience function getShiftedVal<shift>(), and now allows AArch64 scalar 'ADD #-4096' to be accepted to be mapped to SUB #4096. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47310 llvm-svn: 333408
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