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* Reverting r342048, which caused UBSan failures in dsymutil.Wolfgang Pieb2018-09-121-5/+6
| | | | llvm-svn: 342056
* [DWARF] Refactoring range list dumping to fold DWARF v4 functionality into ↵Wolfgang Pieb2018-09-121-6/+5
| | | | | | | | | | | | | v5 handling Eliminating some duplication of rangelist dumping code at the expense of some version-dependent code in dump and extract routines. Reviewer: dblaikie, JDevlieghere, vleschuk Differential revision: https://reviews.llvm.org/D51081 llvm-svn: 342048
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into ↵Ilya Biryukov2018-09-121-1/+1
| | | | | | | | | | | TargetParser." This reverts commit r341982. The change introduced a layering violation. Reverting to unbreak our integrate. llvm-svn: 342023
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-1/+1
| | | | | | | | | | | | | | into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). Differential Revision: https://reviews.llvm.org/D51890 llvm-svn: 341982
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-071-0/+3
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [codeview] Add .cv_string directive for testing purposesReid Kleckner2018-09-071-0/+69
| | | | | | | | | | | The main use case for this directive is to allow assembly writers to write their own FPO data strings without going through the .cv_fpo* directive family. I'm experimenting with different RPN programs to fix PR38857, and I figured I should go ahead and make this directive permanent. llvm-svn: 341712
* [codeview] Improve readobj FPO dumper and pdbutil register namesReid Kleckner2018-09-072-12/+85
| | | | | | The improved dumping helps me investigate PR38857. llvm-svn: 341695
* [RISCV] Fix crash in decoding instruction with unknown floating point ↵Ana Pazos2018-09-071-0/+9
| | | | | | | | | | | | | | | | | | | | rounding mode Summary: Instead of crashing in printFRMArg, decode and warn about invalid instruction. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51705 llvm-svn: 341691
* [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassemblingAna Pazos2018-09-072-0/+11
| | | | | | | | | | | | | | | | | | Summary: RISCVDisassembler should check number of bytes available before reading them. Crash noticed when enabling -DLLVM_USE_SANITIZER=Address. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51708 llvm-svn: 341686
* The initial .text section generated in object files was missing theEric Christopher2018-09-064-1/+69
| | | | | | | | | | | | | | | | | | | | SHF_ARM_PURECODE flag when being built with the -mexecute-only flag. All code sections of an ELF must have the flag set for the final .text section to be execute-only, otherwise the flag gets removed. A HasData flag is added to MCSection to aid in the determination that the section is empty. A virtual setTargetSectionFlags is added to MCELFObjectTargetWriter to allow subclasses to set target specific section flags to be added to sections which we then use in the ARM backend to set SHF_ARM_PURECODE. Patch by Ivan Lozano! Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D48792 llvm-svn: 341593
* [ARC] Prevent InstPrinter from crashing on unknown condition codes.Tatyana Krasnukha2018-09-061-0/+2
| | | | | | | | | | | | | Summary: Instruction printer shouldn't crash with assertions due to incorrect input data. llvm_unreachable is not intended for runtime error handling. Reviewers: petecoup Reviewed By: petecoup Differential Revision: https://reviews.llvm.org/D51728 llvm-svn: 341581
* [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operandsAlex Bradbury2018-09-0616-876/+895
| | | | | | | | | | | | | | | | Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
* [X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.Craig Topper2018-09-062-2/+26
| | | | | | | | | | This basically reverts a change made in r336217, but improves the text of the error message for not allowing IP-relative addressing in 32-bit mode. Fixes PR38826. Patch by Iain Sandoe. llvm-svn: 341512
* [Sparc] allow tls_add/tls_call syntax in assembler parserDaniel Cederman2018-09-031-45/+118
| | | | | | | | | | | | | | | | | Summary: Removing unneeded isCodeGenOnly from tls-specific instructions - TLS_ADD/TLS_LD/TLS_LDX/TLS_CALL. Author: fedor.sergeev Reviewers: jyknight, fedor.sergeev Reviewed By: jyknight Subscribers: dcederman, brad, llvm-commits Differential Revision: https://reviews.llvm.org/D36463 llvm-svn: 341308
* [AVR] Redefine the 'SBR' instruction as an aliasDylan McKay2018-09-011-5/+5
| | | | | | | | | | | This fixes a TableGen warning about duplicate bit patterns. SBR === This is an alias of 'ORI Rd, K'. llvm-svn: 341277
* [RISCV] Fixed SmallVector.h Assertion `idx < size()'Ana Pazos2018-08-301-0/+2
| | | | | | | | | | | | | | | | | | | Summary: RISCVAsmParser needs to handle the case the error message is of specific type, other than the generic Match_InvalidOperand, and the corresponding operand is missing. This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: llvm-commits, jocewei, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX Differential Revision: https://reviews.llvm.org/D50790 llvm-svn: 341104
* [WebAssembly] Made disassembler only use stack instructions.Wouter van Oortmerssen2018-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now uses the StackBased bit from the tablegen defs to identify stack instructions (and ignore register based or non-wasm instructions). Also changed how we store operands, since we now have up to 16 of them per instruction. To not cause static data bloat, these are compressed into a tiny table. + a few other cleanups. Tested: - MCTest - llvm-lit -v `find test -name WebAssembly` Reviewers: dschuff, jgravelle-google, sunfish, tlively Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D51320 llvm-svn: 341081
* [RISCV] Fix r341050Alex Bradbury2018-08-301-3/+0
| | | | | | A few stray lines were accidentally committed. Remove these. llvm-svn: 341053
* [RISCV][NFC] Rework CHECK lines in rvi-aliases-valid.sAlex Bradbury2018-08-301-129/+129
| | | | | | | | | | | | | | | | | | | | | Previously CHECK prefixes weren't defined that can be used to check _only_ the InstPrinter output when generating .s from llvm-mc, or that check _only_ the output after passing the generated object through objdump. This means we can't write useful checks for instructions that reference symbols. Instead, use: CHECK-S Match the .s output with aliases enabled CHECK-S-NOALIAS Match the .s output with aliases disabled CHECK-OBJ Match the objdumped object output with aliases enabled CHECK-OBJ-NOALIAS Match the objdumped object output with aliases enabled CHECK-S-OBJ Match both the .s and objdumped object output with aliases enabled CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with aliases disabled While we're at it, use whitespace consistently within this file. llvm-svn: 341050
* [mips] Add missing instructionsAleksandar Beserminji2018-08-2921-38/+92
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* Revert r340904 "[llvm-mc] - Allow to set custom flags for debug sections."George Rimar2018-08-291-12/+0
| | | | | | | It broke PPC64 BB: http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/23252 llvm-svn: 340906
* [llvm-mc] - Allow to set custom flags for debug sections.George Rimar2018-08-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | I am experimenting with a single split dwarf (.dwo sections in .o files). I want to make linker to ignore .dwo sections in .o, for that I am trying to add SHF_EXCLUDE flag ("E") for them in my asm sample. I found that currently, it is impossible to add any flag for debug sections using llvm-mc. That happens because we have a set of predefined unique sections created early with default flags: https://github.com/llvm-mirror/llvm/blob/master/lib/MC/MCObjectFileInfo.cpp#L391 This patch allows a user to add any flags he wants. I had to edit TargetLoweringObjectFileImpl.cpp to set MetaData type for debug sections. Their kind was Data by default (so they were allocatable) and so after changes introduced by this patch the SHF_ALLOC flag was applied for them, what does not make sense for debug sections. One of OrcJITTests tests failed because of that. Differential revision: https://reviews.llvm.org/D51361 llvm-svn: 340904
* [codeview] Emit labels for .cv_loc immediatelyReid Kleckner2018-08-282-4/+177
| | | | | | | | | | | | | | | Previously we followed the DWARF implementation, which waits until the next instruction or data to emit the label to use in the .debug_loc section. We might want to consider re-evaluating that design choice as well, since it means the .loc skips alignment padding, for better or worse. This was the most minimal fix I could come up with, but we should be able to do a lot of cleanups now that we don't need to save a pending CV location on the CodeViewContext. I plan to do those next, but this immediately fixes an assertion for some of our users. llvm-svn: 340878
* [debuginfo] generate debug info with asm+.fileBrian Cain2018-08-281-0/+24
| | | | | | | | | | | | | | | Summary: For assembly input files, generate debug info even when the .file directive is present, provided it does not include a file-number argument. Fixes PR38695. Reviewers: probinson, sidneym Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D51315 llvm-svn: 340839
* [AMDGPU] Add support for a16 modifiear for gfx9Ryan Taylor2018-08-281-0/+34
| | | | | | | | | | | | | Summary: Adding support for a16 for gfx9. A16 bit replaces r128 bit for gfx9. Change-Id: Ie8b881e4e6d2f023fb5e0150420893513e5f4841 Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50575 llvm-svn: 340831
* [PowerPC][MC] Support expressions in getMemRIX16Encoding.Sean Fertile2018-08-271-0/+38
| | | | | | | | | | Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like lxv/stxv where the offset is an expression. Differential Revision: https://reviews.llvm.org/D51122 llvm-svn: 340761
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-274-72/+71
| | | | | | | | | | | | | | | | | | | | | Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
* [Sparc] Avoid writing outside array in applyFixupDaniel Cederman2018-08-271-0/+6
| | | | | | | | | | | | | | | | Summary: If an object file ends with a relocation that is smaller than 4 bytes we will write outside the Data array and trigger an "Invalid index" assertion. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D50971 llvm-svn: 340736
* [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.Ana Pazos2018-08-241-0/+17
| | | | | | | | | | | | | | | | | | Summary: Missing check for isImm() in some Immediate classes. This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: hiraditya, asb Reviewed By: hiraditya, asb Subscribers: llvm-commits, hiraditya, kito-cheng, shiva0217, rkruppe, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei Differential Revision: https://reviews.llvm.org/D50797 llvm-svn: 340674
* MC: Don't align COFF section contents.Peter Collingbourne2018-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Aligning section contents is not required, but only recommended, by the specification. Microsoft's documentation says (https://docs.microsoft.com/en-us/windows/desktop/debug/pe-format#section-table-section-headers): "For object files, the value should be aligned on a 4-byte boundary for best performance." However, according to my measurements, aligning section contents has a neutral to negative effect on performance. I measured the median run time of 100 links of Chromium's base_unittests on Linux with lld-link and on Windows with link.exe with both aligned and unaligned sections. On Linux I didn't see a measurable performance difference, and on Windows the link was slightly faster with unaligned sections (presumably because on Windows the bottleneck is I/O). Also, the sections created by cl.exe are unaligned, so we should expect tools to broadly accept unaligned sections. Differential Revision: https://reviews.llvm.org/D51149 llvm-svn: 340514
* MC: Teach the COFF object writer to write address-significance tables.Peter Collingbourne2018-08-222-2/+53
| | | | | | | | | The format is the same as in ELF: a sequence of ULEB128-encoded symbol indexes. Differential Revision: https://reviews.llvm.org/D51047 llvm-svn: 340499
* [AArch64] Add Tiny Code Model for AArch64David Green2018-08-221-0/+8
| | | | | | | | | | | | | | This adds the plumbing for the Tiny code model for the AArch64 backend. This, instead of loading addresses through the normal ADRP;ADD pair used in the Small model, uses a single ADR. The 21 bit range of an ADR means that the code and its statically defined symbols need to be within 1MB of each other. This makes it mostly interesting for embedded applications where we want to fit as much as we can in as small a space as possible. Differential Revision: https://reviews.llvm.org/D49673 llvm-svn: 340397
* [WebAssembly] v128.constThomas Lively2018-08-212-2/+16
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-211-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* [AArch64][SVE] Asm: Add SVE System registersSander de Smalen2018-08-202-0/+113
| | | | | | | | | | | | | | | | | | This patch adds system registers for controlling aspects of SVE: - ZCR_EL1 (r/w) visible at EL1 and EL0. - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0. - ZCR_EL3 (r/w) visible at all exception levels. and a system register identifying SVE: - ID_AA64ZFR0_EL1 (r) SVE Feature identifier. Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D50885 llvm-svn: 340158
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-178-0/+645
| | | | | | | | | | | | | | | | | | Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
* [MC] Improve COFF associative section lookupReid Kleckner2018-08-163-0/+36
| | | | | | | | | | | | | | | Handle the case when the symbol is private. Private symbols are not in the COFF object file symbol table, so they aren't inserted into SymbolMap. We can't look up the section of the symbol that way. Instead, get the MCSection from the MCSymbol and map that to the object file section. Print a better error message when the symbol has no section, like when the symbol is undefined. Fixes PR38607 llvm-svn: 339942
* [codeview] Use push_macro to avoid conflicts instead of a prefixReid Kleckner2018-08-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | Summary: This prefix was added in r333421, and it changed our dumper output to say things like "CVRegEAX" instead of just "EAX". That's a functional change that I'd rather avoid. I tested GCC, Clang, and MSVC, and all of them support #pragma push_macro. They don't issue warnings whem the macro is not defined either. I don't have a Mac so I can't test the real termios.h header, but I looked at the termios.h sources online and looked for other conflicts. I saw only the CR* macros, so those are the ones we work around. Reviewers: zturner, JDevlieghere Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50851 llvm-svn: 339907
* [MC][X86] Enhance X86 Register expression handling to more closely match GCC.Nirav Dave2018-08-161-7/+11
| | | | | | | | | | | | | | | | Allow the comparison of x86 registers in the evaluation of assembler directives. This generalizes and simplifies the extension from r334022 to catch another case found in the Linux kernel. Reviewers: rnk, void Reviewed By: rnk Subscribers: hiraditya, nickdesaulniers, llvm-commits Differential Revision: https://reviews.llvm.org/D50795 llvm-svn: 339895
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-08-134-61/+62
| | | | | | This reverts commit 917a99b71ce21c975be7bfbf66f4040f965d9f3c. llvm-svn: 339630
* [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode ↵Craig Topper2018-08-131-36/+48
| | | | | | | | | | | | | | | | selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same. While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day. The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with. While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them. Fixes PR38537. llvm-svn: 339622
* Check for tied operandsSid Manning2018-08-131-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D50592 llvm-svn: 339567
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-104-62/+61
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: jfb, llvm-commits, aheejin, eraman, jgravelle-google, sbc100 Differential Revision: https://reviews.llvm.org/D50568 llvm-svn: 339474
* [RISC-V] Fixed alias for addi x2, x2, 0Ana Pazos2018-08-091-0/+3
| | | | | | | | A missing check for non-zero immediate in MCOperandPredicate caused c.addi16sp sp, 0 to be selected which is not a valid instruction. llvm-svn: 339381
* [RISCV] Add "lla" pseudo-instruction to assemblerRoger Ferrer Ibanez2018-08-092-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314
* [DWARF] Unclamp line table version on Darwin for v5 and later.Jonas Devlieghere2018-08-082-4/+0
| | | | | | | | | On Darwin we pin the DWARF line tables to version 2. Stop doing so for DWARF v5 and later. Differential revision: https://reviews.llvm.org/D49381 llvm-svn: 339288
* [RISCV] Add mnemonic alias: move, sbreak and scall.Alex Bradbury2018-08-081-0/+11
| | | | | | | | | Further improve compatibility with the GNU assembler. Differential Revision: https://reviews.llvm.org/D50217 Patch by Kito Cheng. llvm-svn: 339255
* [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], ↵Alex Bradbury2018-08-085-1/+81
| | | | | | | | | | | | sra[w], slt and sltu with immediate Match the GNU assembler in supporting immediate operands for these instructions even when the reg-reg mnemonic is used. Differential Revision: https://reviews.llvm.org/D50046 Patch by Kito Cheng. llvm-svn: 339252
* MC: Redirect .addrsig directives referring to private (.L) symbols to the ↵Peter Collingbourne2018-08-061-7/+7
| | | | | | | | | | | | | section symbol. This matches our behaviour for regular (i.e. relocated) references to private symbols and therefore avoids needing to unnecessarily write address-significant .L symbols to the object file's symbol table, which can interfere with stack traces. Fixes check-cfi after r339050. llvm-svn: 339066
* ARM-MachO: don't add Thumb bit for addend to non-external relocation.Tim Northover2018-08-062-0/+22
| | | | | | | | | ld64 supplies its own Thumb bit for Thumb functions, and intentionally zeroes out that part of any addend in an object file. But it only does that for symbols marked N_EXT -- i.e. external symbols. So LLVM should avoid setting that extra bit in other cases. llvm-svn: 339007
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