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* [AMDGPU] Implement AMDGPUMCInstrAnalysisScott Linder2019-03-051-0/+42
| | | | | | | | | Implement MCInstrAnalysis for AMDGPU, with default implementations save for `evaluateBranch`. Differential Revision: https://reviews.llvm.org/D58400 llvm-svn: 355373
* [MC] Teach ELFObjectWriter that parse-time variables do not appear inNirav Dave2019-03-041-0/+3
| | | | | | symbol table. llvm-svn: 355325
* [WebAssembly] Add support for data sections in the assembler.Wouter van Oortmerssen2019-03-042-2/+108
| | | | | | | | | | | | | | | | Summary: This is quite minimal so far, introduce them with .section, fill them with .int8 or .asciz, end with .size Reviewers: dschuff, sbc100, aheejin Subscribers: jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58660 llvm-svn: 355321
* [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, ↵Dmitry Preobrazhensky2019-03-044-22/+59
| | | | | | | | | | | | v_readlane_b32 and v_writelane_b32 See bug 40662: https://bugs.llvm.org/show_bug.cgi?id=40662 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D58713 llvm-svn: 355312
* [DWARF] Make -g with empty assembler source work better.Paul Robinson2019-03-011-1/+1
| | | | | | | | | | | | | This was sometimes causing clang or llvm-mc to crash, and in other cases could emit a bogus DWARF line-table header. I did an interim patch in r352541; this patch should be a cleaner and more complete fix, and retains the test. Addresses PR40538. Differential Revision: https://reviews.llvm.org/D58750 llvm-svn: 355226
* [llvm-readobj] Display section names for STT_SECTION symbols.Matt Davis2019-03-016-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch will obtain the section name for symbols that refer to a section. Prior to this patch the Name field for STT_SECTIONs was blank, now it is populated. Before: ``` Symbol table '.symtab' contains 6 entries: Num: Value Size Type Bind Vis Ndx Name 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1 2: 0000000000000000 0 SECTION LOCAL DEFAULT 3 3: 0000000000000000 0 SECTION LOCAL DEFAULT 4 4: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_ 5: 0000000000000000 0 TLS GLOBAL DEFAULT UND sym ``` With this patch: ``` Symbol table '.symtab' contains 6 entries: Num: Value Size Type Bind Vis Ndx Name 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1 .text 2: 0000000000000000 0 SECTION LOCAL DEFAULT 3 .data 3: 0000000000000000 0 SECTION LOCAL DEFAULT 4 .bss 4: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_ 5: 0000000000000000 0 TLS GLOBAL DEFAULT UND sym ``` This fixes PR40788 Reviewers: jhenderson, rupprecht, espindola Reviewed By: rupprecht Subscribers: emaste, javed.absar, arichardson, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58796 llvm-svn: 355207
* bpf: disassembler support for XADD under sub-register modeJiong Wang2019-02-282-1/+5
| | | | | | | | | | | | Like the other load/store instructions, "w" register is preferred when disassembling BPF_STX | BPF_W | BPF_XADD. v1 -> v2: - Updated testcase insn-unit.s (Yonghong) Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 355127
* [WebAssembly] Remove uses of ThreadModelThomas Lively2019-02-2811-35/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In the clang UI, replaces -mthread-model posix with -matomics as the source of truth on threading. In the backend, replaces -thread-model=posix with the atomics target feature, which is now collected on the WebAssemblyTargetMachine along with all other used features. These collected features will also be used to emit the target features section in the future. The default configuration for the backend is thread-model=posix and no atomics, which was previously an invalid configuration. This change makes the default valid because the thread model is ignored. A side effect of this change is that objects are never emitted with passive segments. It will instead be up to the linker to decide whether sections should be active or passive based on whether atomics are used in the final link. Reviewers: aheejin, sbc100, dschuff Subscribers: mehdi_amini, jgravelle-google, hiraditya, sunfish, steven_wu, dexonsmith, rupprecht, jfb, jdoerfert, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D58742 llvm-svn: 355112
* [AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operandsDmitry Preobrazhensky2019-02-273-23/+206
| | | | | | | | | | See bug 37943: https://bugs.llvm.org/show_bug.cgi?id=37943 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D58287 llvm-svn: 354974
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of ↵Dmitry Preobrazhensky2019-02-275-16/+86
| | | | | | | | | | | | instructions s_set_gpr_idx_on and s_set_gpr_idx_mode See bug 39331: https://bugs.llvm.org/show_bug.cgi?id=39331 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D58288 llvm-svn: 354969
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-255-0/+7
| | | | | | | | - Add LLVM backend support for Cortex-A76 and Cortex-A76AE - Documentation can be found at https://developer.arm.com/products/processors/cortex-a/cortex-a76 llvm-svn: 354788
* Fixed typos in tests: s/CEHCK/CHECK/Dmitri Gribenko2019-02-254-7/+7
| | | | | | | | | | | | Reviewers: ilya-biryukov Subscribers: sanjoy, sdardis, javed.absar, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58608 llvm-svn: 354781
* [ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham2019-02-253-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More or less all the instructions defined in the v8.2a full-fp16 extension are defined as UNPREDICTABLE if you put them in an IT block (Thumb) or use with any condition other than AL (ARM). LLVM didn't know that, and was happy to conditionalise them. In order to force these instructions to count as not predicable, I had to make a small Tablegen change. The code generation back end mostly decides if an instruction was predicable by looking for something it can identify as a predicate operand; there's an isPredicable bit flag that overrides that check in the positive direction, but nothing that overrides it in the negative direction. (I considered the alternative approach of actually removing the predicate operand from those instructions, but thought that it would be more painful overall for instructions differing only in data type to have different shapes of operand list. This way, the only code that has to notice the difference is the if-converter.) So I've added an isUnpredicable bit alongside isPredicable, and set that bit on the right subset of FP16 instructions, and also on the VSEL, VMAXNM/VMINNM and VRINT[ANPM] families which should be unpredicable for all data types. I've included a couple of representative regression tests, both of which previously caused an fp16 instruction to be conditionalised in ARM state and (with -arm-no-restrict-it) to be put in an IT block in Thumb. Reviewers: SjoerdMeijer, t.p.northover, efriedma Reviewed By: efriedma Subscribers: jdoerfert, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57823 llvm-svn: 354768
* [WebAssembly] Remove unneeded MCSymbolRefExpr variantsSam Clegg2019-02-223-11/+11
| | | | | | | | | | | | | | We record the type of the symbol (event/function/data/global) in the MCWasmSymbol and so it should always be clear how to handle a relocation based on the symbol itself. The exception is a function which still needs the special @TYPEINDEX then the relocation contains the signature rather than the address of the functions. Differential Revision: https://reviews.llvm.org/D58472 llvm-svn: 354697
* [WebAssembly] MC: Handle aliases of aliasesSam Clegg2019-02-221-0/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D58417 llvm-svn: 354694
* [RISCV] Add implied zero offset load/store alias patternsAlex Bradbury2019-02-218-0/+99
| | | | | | | | | | Allow load/store instructions with implied zero offset for compatibility with GNU assembler. Differential Revision: https://reviews.llvm.org/D57141 Patch by James Clarke. llvm-svn: 354581
* [RISCV] Implement pseudo instructions for load/store from a symbol address.Kito Cheng2019-02-208-5/+98
| | | | | | | | | | | | | Summary: Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address. Reviewers: asb, apazos, rogfer01, jrtc27 Differential Revision: https://reviews.llvm.org/D50496 llvm-svn: 354430
* [WebAssembly] Fix load/store name detection for atomic instructionsHeejin Ahn2019-02-201-0/+149
| | | | | | | | | | | | | | | | | | | | Summary: Fixed a bug in the routine in AsmParser that determines whether the current instruction is a load or a store. Atomic instructions' prefixes are not `atomic_` but `atomic.`, and all atomic instructions are also memory instructions. Also fixed the printing format of atomic instructions to match other memory instructions and added encoding tests for atomic instructions. Reviewers: aardappel, tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58337 llvm-svn: 354419
* [WebAssembly] Fixed disassembler not knowing about OPERAND_EVENTWouter van Oortmerssen2019-02-201-0/+3
| | | | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58414 llvm-svn: 354416
* [WebAssembly] Update MC for bulk memoryThomas Lively2019-02-1911-37/+62
| | | | | | | | | | | | | | | | | | Summary: Rename MemoryIndex to InitFlags and implement logic for determining data segment layout in ObjectYAML and MC. Also adds a "passive" flag for the .section assembler directive although this cannot be assembled yet because the assembler does not support data sections. Reviewers: sbc100, aardappel, aheejin, dschuff Subscribers: jgravelle-google, hiraditya, sunfish, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57938 llvm-svn: 354397
* X86AsmParser AVX-512: Return error instead of hitting assertCraig Topper2019-02-191-0/+3
| | | | | | | | | | When parsing a sequence of tokens beginning with {, it will hit an assert and crash if the token afterwards is not an identifier. Instead of this, return a more verbose error as seen elsewhere in the function. Patch by Brandon Jones (BrandonTJones) Differential Revision: https://reviews.llvm.org/D57375 llvm-svn: 354356
* [RISCV] Add assembler support for LA pseudo-instructionAlex Bradbury2019-02-152-2/+69
| | | | | | | | | | This patch also introduces the emitAuipcInstPair helper, which is then used for both emitLoadAddress and emitLoadLocalAddress. Differential Revision: https://reviews.llvm.org/D55325 Patch by James Clarke. llvm-svn: 354111
* [RISCV] Support assembling %got_pcrel_hi operatorAlex Bradbury2019-02-152-6/+40
| | | | | | | Differential Revision: https://reviews.llvm.org/D55279 Patch by James Clarke. llvm-svn: 354110
* [WebAssembly] memory.fillThomas Lively2019-02-131-0/+18
| | | | | | | | | | | | | | | | Summary: memset lowering, fix argument types in memcpy lowering, and test encodings. Depends on D57736. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57791 llvm-svn: 353986
* [MC] Make symbol version errors non-fatalReid Kleckner2019-02-132-2/+2
| | | | | | | | | We stil don't have a source location, which is pretty lame, but at least we won't tell the user to file a clang bug report anymore. Fixes PR40712 llvm-svn: 353907
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-083-0/+194
| | | | | | | | | | See bug 39293: https://bugs.llvm.org/show_bug.cgi?id=39293 Reviewers: artem.tamazov, rampitec Differential Revision: https://reviews.llvm.org/D57889 llvm-svn: 353524
* [AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and ↵Dmitry Preobrazhensky2019-02-081-4/+10
| | | | | | | | | | | | | | stepping numbers Added the following Code Object v3 symbols: .amdgcn.gfx_generation_minor .amdgcn.gfx_generation_stepping Reviewers: artem.tamazov, kzhuravl Differential Revision: https://reviews.llvm.org/D57826 llvm-svn: 353515
* [WebAssembly] Fixed Disassembler ignoring endian swap on big endian.Wouter van Oortmerssen2019-02-081-3/+1
| | | | | | | | | | | | | | Summary: This fixes: https://bugs.llvm.org/show_bug.cgi?id=40620 Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57933 llvm-svn: 353496
* [WebAssembly] Fix imported function symbol names that differ from their ↵Dan Gohman2019-02-072-1/+33
| | | | | | | | | | | | | | import names in the .o format Add a flag to allow symbols to have a wasm import name which differs from the linker symbol name, allowing the linker to link code using the import_module attribute. This is the MC/Object portion of the patch. Differential Revision: https://reviews.llvm.org/D57632 llvm-svn: 353474
* [BPF] add code-gen support for JMP32 instructionsJiong Wang2019-02-071-0/+47
| | | | | | | | | | | | | | | | | | | | | | | JMP32 instructions has been added to eBPF ISA. They are 32-bit variants of existing BPF conditional jump instructions, but the comparison happens on low 32-bit sub-register only, therefore some unnecessary extensions could be saved. JMP32 instructions will only be available for -mcpu=v3. Host probe hook has been updated accordingly. JMP32 instructions will only be enabled in code-gen when -mattr=+alu32 enabled, meaning compiling the program using sub-register mode. For JMP32 encoding, it is a new instruction class, and is using the reserved eBPF class number 0x6. This patch has been tested by compiling and running kernel bpf selftests with JMP32 enabled. Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 353384
* [WebAssembly] Add symbol flag to the binary format llvm.usedSam Clegg2019-02-071-0/+21
| | | | | | | | | | | | | | Summary: Rather than add a new attribute See https://github.com/WebAssembly/tool-conventions/issues/64 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57864 llvm-svn: 353360
* [WebAssembly] Expand symbol flags shown by llvm-objdump --symbolsSam Clegg2019-02-073-13/+32
| | | | | | Differential Revision: https://reviews.llvm.org/D57861 llvm-svn: 353357
* AArch64: annotate atomics with dropped acquire semantics when printing.Tim Northover2019-02-061-0/+190
| | | | | | | | | | | A quirk of the v8.1a spec is that when the writeback regiser for an atomic read-modify-write instruction is wzr/xzr, the instruction no longer enforces acquire ordering. However, it's still written with the misleading 'a' mnemonic. So this adds an annotation when disassembling such instructions, mentioning the change. llvm-svn: 353303
* [WebAssembly] Add a comment about why v128.const test was disabled (NFC)Heejin Ahn2019-02-051-0/+2
| | | | llvm-svn: 353236
* [WebAssembly] Disable a v128.const test line temporarilyHeejin Ahn2019-02-051-1/+1
| | | | | | | | r353131 caused failures in v128.const test for clang-ppc64be-linux-lnt and clang-s390x-linux bots. This temporarily disables that line until it is fixed. llvm-svn: 353234
* [MC] Don't error on numberless .file directives on MachOReid Kleckner2019-02-052-8/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: Before r349976, MC ignored such directives when producing an object file and asserted when re-producing textual assembly output. I turned this assertion into a hard error in both cases in r349976, but this makes it unnecessarily difficult to write a single assembly file that supports both MachO and other object formats that support .file. A user reported this as PR40578, and we decided to go back to ignoring the directive. Fixes PR40578 Reviewers: mstorsjo Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57772 llvm-svn: 353218
* Move some llvm-mc tests where they belongMatt Arsenault2019-02-052-0/+46
| | | | llvm-svn: 353211
* [WebAssembly] Make disassembler always emit most canonical name.Wouter van Oortmerssen2019-02-052-4/+11
| | | | | | | | | | | | | | | | | | | | | Summary: There are a few instructions that all map to the same opcode, so when disassembling, we have to pick one. That was just the first one before (the except_ref variant in the case of "call"), now it is the one marked as IsCanonical in tablegen, or failing that, the shortest name (which is typically the "canonical" one). Also introduced a canonical "end" instruction for this purpose. Reviewers: dschuff, tlively Subscribers: sbc100, jgravelle-google, aheejin, llvm-commits, sunfish Tags: #llvm Differential Revision: https://reviews.llvm.org/D57713 llvm-svn: 353131
* [WebAssembly] MC: Mark more function aliases as functionsSam Clegg2019-02-041-0/+32
| | | | | | | | | | | | | Aliases of functions are now marked as function symbols even if they are bitcast to some other other non-function type. This is important for WebAssembly where object and function symbols can't alias each other. Fixes PR38866 Differential Revision: https://reviews.llvm.org/D57538 llvm-svn: 353109
* [llvm-readobj] Report more WebAssembly symbol infoSam Clegg2019-02-041-0/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D57695 llvm-svn: 353104
* [WebAssembly] Make segment/size/type directives optional in asmWouter van Oortmerssen2019-02-044-20/+0
| | | | | | | | | | | | | | | | | | | | Summary: These were "boilerplate" that repeated information already present in .functype and end_function, that needed to be repeated to Please the particular way our object writing works, and missing them would generate errors. Instead, we generate the information for these automatically so the user can concern itself with writing more canonical wasm functions that always work as expected. Reviewers: dschuff, sbc100 Subscribers: jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57546 llvm-svn: 353067
* [WebAssembly] Rename relocations from R_WEBASSEMBLY_ to R_WASM_Sam Clegg2019-02-0413-58/+58
| | | | | | | | | | | | | | | | See https://github.com/WebAssembly/tool-conventions/pull/95. This is less typing and IMHO more readable, and it also fits with our naming around the binary format which tends to use the short name. e.g. include/llvm/BinaryFormat/Wasm.h tools/llvm-objdump/WasmDump.cpp etc.. Differential Revision: https://reviews.llvm.org/D57611 llvm-svn: 353062
* [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two ↵Craig Topper2019-02-0410-216/+216
| | | | | | | | | | arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. llvm-svn: 353061
* [X86] Print %st(0) as %st when its implicit to the instruction. Continue ↵Craig Topper2019-02-048-233/+233
| | | | | | | | printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
* Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses ↵Craig Topper2019-02-0411-319/+319
| | | | | | | | | | as the clobber name to make MS inline asm work correctly" Looking into gcc and objdump behavior more this was overly aggressive. If the register is encoded in the instruction we should print %st(0), if its implicit we should print %st. I'll be making a more directed change in a future patch. llvm-svn: 353013
* [X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber ↵Craig Topper2019-02-0311-319/+319
| | | | | | | | | | | | | | | | | | | name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
* [X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>Craig Topper2019-02-0220-170/+15824
| | | | | | | | | | | | | | | | | | | | | | Summary: NFC. Adding MC regressions tests to cover all the SSE ISA sets as follows: SSE, SSE2, SSE3, SSE4, SSE42, SSEMXCSR, SSE_PREFETCH, SSSE3 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. See revision: https://reviews.llvm.org/D39952 Patch by Gadi Haber and Wang Tianqing Reviewers: RKSimon, zvi, craig.topper, AndreiGrischenko, gadi.haber, LuoYuanke Reviewed By: craig.topper Subscribers: jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D40387 llvm-svn: 352955
* [WebAssembly] Add codegen support for the import_field attributeDan Gohman2019-02-011-2/+2
| | | | | | | | | This adds the LLVM side of https://reviews.llvm.org/D57602 -- the import_field attribute. See that patch for details. Differential Revision: https://reviews.llvm.org/D57603 llvm-svn: 352931
* [WebAssembly] MC: Fix for outputing wasm object to /dev/nullSam Clegg2019-01-311-0/+10
| | | | | | | | Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57479 llvm-svn: 352806
* [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment ↵Shiva Chen2019-01-301-0/+105
| | | | | | | | | | | | | | | | | | | | when linker relaxation enabled Linker relaxation may change code size. We need to fix up the alignment of alignment directive in text section by inserting Nops and R_RISCV_ALIGN relocation type. So then linker could satisfy the alignment by removing Nops. To do this: 1. Add shouldInsertExtraNopBytesForCodeAlign target hook to calculate the Nops we need to insert. 2. Add shouldInsertFixupForCodeAlign target hook to insert R_RISCV_ALIGN fixup type. Differential Revision: https://reviews.llvm.org/D47755 llvm-svn: 352616
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