summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86][MC] no error diagnostic for out-of-range jrcxz/jecxz/jcxzAlexey Lapshin2019-11-262-1/+27
| | | | | | | | | | | | | | Fix for PR24072: X86 instructions jrcxz/jecxz/jcxz performs short jumps if rcx/ecx/cx register is 0 The maximum relative offset for a forward short jump is 127 Bytes (0x7F). The maximum relative offset for a backward short jump is 128 Bytes (0x80). Gnu assembler warns when the distance of the jump exceeds the maximum but llvm-as does not. Patch by Konstantin Belochapka and Alexey Lapshin Differential Revision: https://reviews.llvm.org/D70652
* [mips] Split test into MIPS and microMIPS parts. NFCSimon Atanasyan2019-11-252-26/+34
|
* Reduce the number of iterations in testcase. (NFC)Adrian Prantl2019-11-211-2/+2
|
* [mips] Rename test case. NFCSimon Atanasyan2019-11-211-0/+0
|
* [mips] Remove addresses from the test case. NFCSimon Atanasyan2019-11-211-40/+40
| | | | It reduces "diff" after addition more tests in the future.
* Fix an offset underflow bug in DwarfExpression when describing small values ↵Adrian Prantl2019-11-201-3/+3
| | | | | | | | | | | | | | | | | | with subregisters DwarfExpression::addMachineReg() knows how to build a larger register that isn't expressible in DWARF by combining multiple subregisters. However, if the entire value fits into just one subregister, it would still emit the other subregisters, leading to all sorts of inconsistencies down the line. This patch fixes that by moving an already existing(!) check whether the subregister's offset is before the end of the value to the right place. rdar://problem/57294211 Differential Revision: https://reviews.llvm.org/D70508
* Fixup AVR tests to reflect changes in addend format in llvm-objdumpDavid Bozier2019-11-198-14/+14
| | | | | | | | | | | | | | Summary: Changes to llvm-objdump made in D69997 Reviewers: thakis, jhenderson, grimar Reviewed By: thakis Subscribers: dylanmckay, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70438
* [llvm-objdump] Print relocation addends in hexadecimalDavid Bozier2019-11-195-40/+40
| | | | | | | | | | | | | | Summary: Matches GNU objdump. Makes debugging easier for me as I'm working out addresses from symbol+addend, so it would be good to be calculating in a single format. Reviewers: MaskRay, grimar, jhenderson, bd1976llvm Reviewed By: jhenderson Subscribers: sdardis, jrtc27, atanasyan, rupprecht, seiya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69997
* [AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodesDmitry Preobrazhensky2019-11-186-2/+173
| | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43712 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D70170
* [RISCV] Add assembly mnemonic spell checkingSimon Cook2019-11-181-0/+32
| | | | | | | | | | | | | | | | Summary: This allows the assembler to suggest alternative assembly mnemonics when an invalid one has been provided. Reviewers: asb, lenary, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69894
* MCObjectStreamer: assign MCSymbols in the dummy fragment to offset 0.James Y Knight2019-11-161-11/+15
| | | | | | | | | | | | | | | | | In MCObjectStreamer, when there is no current fragment, initially symbols are created in a "pending" state and assigned to a dummy empty fragment. Previously, they were not being assigned an offset, and thus evaluateAbsolute would fail if trying to evaluate an expression 'a - b', where both 'a' and 'b' were in this pending state. Also slightly refactored the EmitLabel overload which takes an MCFragment for clarity. Fixes: https://llvm.org/PR41825 Differential Revision: https://reviews.llvm.org/D70062
* [mips] Enable `la` pseudo instruction on 64-bit arch.Simon Atanasyan2019-11-152-8/+485
| | | | | | | This patch makes LLVM compatible with GAS. It accepts `la` pseudo instruction on arch with 64-bit pointers and just shows a warning. Differential Revision: https://reviews.llvm.org/D70202
* [mips] Do not emit R_MIPS_JALR for sym+offset in case of O32 ABISimon Atanasyan2019-11-151-61/+61
| | | | | | | | | | O32 ABI uses relocations in REL format. Relocation's addend is written in place. R_MIPS_JALR relocation points to the `jalr` instruction which does not have a place to store the relocation addend. So it's impossible to save non-zero "offset". This patch blocks emission of `R_MIPS_JALR` relocations in such cases. Differential Revision: https://reviews.llvm.org/D70201
* [mips] Add test to check ELF output for JAL XGOT expansion. NFCSimon Atanasyan2019-11-131-0/+216
|
* [mips] Add tests to check `jal sym+offset`. NFCSimon Atanasyan2019-11-131-59/+401
|
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-132-8/+22
| | | | | | The instruction definition has been retroactively expanded to allow for an alias for '[xN, 0]!' as '[xN]!'. That wouldn't make sense on LDR, but does for LDRA.
* ARM: Don't emit R_ARM_NONE relocations to compact unwinding decoders in ↵Peter Collingbourne2019-11-121-24/+23
| | | | | | | | | | | | | | | | | | | | | | | | .ARM.exidx on Android. These relocations are specified by the ARM EHABI (section 6.3). As I understand it, their purpose is to accommodate unwinder implementations that wish to reduce code size by placing the implementations of the compact unwinding decoders in a separate translation unit, and using extern weak symbols to refer to them from the main unwinder implementation, so that they are only linked when something in the binary needs them in order to unwind. However, neither of the unwinders used on Android (libgcc, LLVM libunwind) use this technique, and in fact emitting these relocations ends up being counterproductive to code size because they cause a copy of the unwinder to be statically linked into most binaries, regardless of whether it is actually needed. Furthermore, these relocations create circular dependencies (between libc and the unwinder) in cases where the unwinder is dynamically linked and libc contains compact unwind info. Therefore, deviate from the EHABI here and stop emitting these relocations on Android. Differential Revision: https://reviews.llvm.org/D70027
* [PowerPC] Implementing overflow version for XO-Form instructionsStefan Pintile2019-11-114-43/+379
| | | | | | | | | | | | | | | The Overflow version of XO-Form instruction uses the SO, OV and OV32 special registers. This changes modifies existing multiclasses and instruction definitions to allow for the use of the XER register to record the various types if overflow from possible add, subtract and multiply instructions. It then modifies the existing instructions as to use these multiclasses as needed. Patch By: Kamau Bridgeman Differential Revision: https://reviews.llvm.org/D66902
* DebugInfo: Do not create a debug_macinfo section if no CUs have associated ↵David Blaikie2019-11-081-20/+14
| | | | | | macros Patch based on Sourabh Singh's D69839 patch.
* [MC] Emit unused undefined symbol even if its binding is not setFangrui Song2019-11-082-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | Recommit r373168, which was reverted by r373242. This actually exposed a boringssl bug which has been fixed for more than one month. For the following two cases, we currently suppress the symbols. This patch emits them (compatible with GNU as). * `test2_a = undef`: if `undef` is otherwise unused. * `.hidden hidden`: if `hidden` is unused. This is the main point of the patch, because omitting the symbol would cause a linker semantic difference. It causes a behavior change that is not compatible with GNU as: .weakref foo1, bar1 When neither foo1 nor bar1 is used, we now emit bar1, which is arguably more consistent. Another change is that we will emit .TOC. for .TOC.@tocbase . For this directive, suppressing .TOC. can be seen as a size optimization, but we choose to drop it for simplicity and consistency.
* DebugInfo: Use separate macinfo contributions for each CUDavid Blaikie2019-11-081-11/+11
| | | | | | | | | | | | | | | | The macinfo support was broken for LTO situations, by terminating macinfo lists only once - multiple macinfo contributions were correctly labeled, but they all continued/flowed into later contributions until only one terminator appeared at the end of the section. Correctly terminate each contribution & fix the parsing to handle this situation too. The parsing fix is also necessary for dumping linked binaries - the previous code would stop at the end of the first contribution - missing all later contributions in a linked binary. It'd be nice to improve the dumping to print the offsets of each contribution so it'd be easier to know which CU AT_macro_info refers to which macinfo contribution.
* [AMDGPU][MC] Corrected src0 for v_movrelsd_b32 and v_movrelsd_2_b32Dmitry Preobrazhensky2019-11-082-0/+10
| | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=40903 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D69888
* [RISCV] Fix evaluation of %pcrel_loRoger Ferrer Ibanez2019-11-081-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following testcase function: .Lpcrel_label1: auipc a0, %pcrel_hi(other_function) addi a1, a0, %pcrel_lo(.Lpcrel_label1) .p2align 2 # Causes a new fragment to be emitted .type other_function,@function other_function: ret exposes an odd behaviour in which only the %pcrel_hi relocation is evaluated but not the %pcrel_lo. $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - <stdin>: file format ELF64-riscv Disassembly of section .text: 0000000000000000 function: 0: 17 05 00 00 auipc a0, 0 4: 93 05 05 00 mv a1, a0 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 0000000000000008 other_function: 8: 67 80 00 00 ret The reason seems to be that in RISCVAsmBackend::shouldForceRelocation we only consider the fragment but in RISCVMCExpr::evaluatePCRelLo we consider the section. This usually works but there are cases where the section may still be the same but the fragment may be another one. In that case we end forcing a %pcrel_lo relocation without any %pcrel_hi. This patch makes RISCVAsmBackend::shouldForceRelocation use the section, if any, to determine if the relocation must be forced or not. Differential Revision: https://reviews.llvm.org/D60657
* [mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` sectionSimon Atanasyan2019-11-071-0/+6
| | | | Differential Revision: https://reviews.llvm.org/D69851
* [mips] Support `octeon+` CPU in the `.set arch=` directiveSimon Atanasyan2019-11-071-0/+4
| | | | Differential Revision: https://reviews.llvm.org/D69850
* [mips] Implement Octeon+ `saa` and `saad` instructionsSimon Atanasyan2019-11-078-0/+280
| | | | | | | | | | | | | | | `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
* [AMDGPU] return Fail instead of SolfFail from addOperand()Stanislav Mekhanoshin2019-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | addOperand() method of AMDGPU disassembler returns SoftFail on error. All instances which may lead to that place are an impossible encdoing, not something which is possible to encode, but semantically incorrect as described for SoftFail. Then tablegen generates a check of the following form: if (Decode...(..) == MCDisassembler::Fail) { return MCDisassembler::Fail; } Since we can only return Success and SoftFail that is dead code as detected by the static code analyzer. Solution: return Fail as it should be. See https://bugs.llvm.org/show_bug.cgi?id=43886 Differential Revision: https://reviews.llvm.org/D69819
* [SystemZ] Improve handling of huge PC relative immediate offsets.Jonas Paulsson2019-11-041-0/+6
| | | | | | | | | | | | | | | Demand that an immediate offset to a PC relative address fits in 32 bits, or else load it into a register and perform a separate add. Verify in the assembler that such immediate offsets fit the bitwidth. Even though the final address of a Load Address Relative Long may fit in 32 bits even with a >32 bit offset (depending on where the symbol lives relative to PC), the GNU toolchain demands the offset by itself to be in range. This patch adapts the same behavior for llvm. Review: Ulrich Weigand https://reviews.llvm.org/D69749
* [mips] Move test case for Octeon instructions to cnmips sub-folder. NFCSimon Atanasyan2019-11-041-0/+0
|
* [mips] Add disassembler tests for `octeon` CPU. NFCSimon Atanasyan2019-11-042-0/+62
|
* [mips] Add disassembler tests for `sigrie` instruction. NFCSimon Atanasyan2019-11-044-0/+4
|
* [WebAssembly] Add experimental SIMD dot product instructionThomas Lively2019-11-011-0/+3
| | | | | | | | | | | | | | | | | | | Summary: This instruction is not merged to the spec proposal, but we need it to be implemented in the toolchain to experiment with it. It is available only on an opt-in basis through a clang builtin. Defined in https://github.com/WebAssembly/simd/pull/127. Depends on D69696. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69697
* [WebAssembly] SIMD integer min and max instructionsThomas Lively2019-10-311-0/+36
| | | | | | | | | | | | | | | | | | | | | | Summary: Introduces a clang builtins and LLVM intrinsics representing integer min/max instructions. These instructions have not been merged to the SIMD spec proposal yet, so they are currently opt-in only via builtins and not produced by general pattern matching. If these instructions are accepted into the spec proposal the builtins and intrinsics will be replaced with normal pattern matching. Defined in https://github.com/WebAssembly/simd/pull/27. Reviewers: aheejin Reviewed By: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69696
* [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64Dmitry Preobrazhensky2019-10-282-0/+264
| | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43747 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D69348
* Revert "[ARM] Uses "Sun Style" syntax for section switching"Jian Cai2019-10-251-13/+0
| | | | This reverts commit 03de2f84fc4acf06c719cd007b5459c9d4d0a20c.
* [ARM] Uses "Sun Style" syntax for section switchingJian Cai2019-10-251-0/+13
| | | | | | | | | | | | | | | | Summary: Support "Sun Style" syntax for section switching ("#alloc,#write" etc). https://bugs.llvm.org/show_bug.cgi?id=43759 Reviewers: peter.smith, eli.friedman, kristof.beyls, t.p.northover Reviewed By: peter.smith Subscribers: MaskRay, llozano, manojgupta, nickdesaulniers, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69296
* Always flush pending errors in MCAsmParserJoerg Sonnenberger2019-10-251-0/+4
| | | | This has become visible with the --fatal-warnings support.
* [mips] Use `expandLoadAddress` for JAL expansionSimon Atanasyan2019-10-231-0/+93
| | | | | - Reduce code duplication - Get partial support of JAL expansion for XGOT.
* [mips] Implement `la` macro expansion for N32 ABISimon Atanasyan2019-10-231-10/+83
|
* [mips] Add tests to check `la / dla` expansion in XGOT cases. NFCSimon Atanasyan2019-10-232-0/+196
|
* [mips] Reformat `la / dla` expansion test cases. NFCSimon Atanasyan2019-10-232-96/+149
|
* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-233-19/+41
| | | | | | | | | | MipsMCAsmInfo was using '$' prefix for Mips32 and '.L' for Mips64 regardless of -target-abi option. By passing MCTargetOptions to MCAsmInfo we can find out Mips ABI and pick appropriate prefix. Tags: #llvm, #clang, #lldb Differential Revision: https://reviews.llvm.org/D66795
* [X86] Fix register parsing in .seh_* in Intel syntaxReid Kleckner2019-10-181-0/+46
| | | | | | | | | | Previously, the parser checked for a '%' prefix to indicate a register. In Intel syntax mode, LLVM does not print a '%' prefix on registers, so LLVM could not parse its own assembly output. Instead, require that register numbers be integer literals, or at least start with an integer literal, which is consistent with .cfi_* directive register parsing. llvm-svn: 375287
* [WebAssembly] Allow multivalue signatures in object filesThomas Lively2019-10-1810-25/+38
| | | | | | | | | | | | | | | | | Summary: Also changes the wasm YAML format to reflect the possibility of having multiple return types and to put the returns after the params for consistency with the binary encoding. Reviewers: aheejin, sbc100 Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, arphaman, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69156 llvm-svn: 375283
* [AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32Dmitry Preobrazhensky2019-10-184-0/+60
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43608 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D69096 llvm-svn: 375241
* [AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwaDmitry Preobrazhensky2019-10-181-0/+5
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43607 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D69095 llvm-svn: 375231
* [AArch64] Adding support for PMMIR_EL1 registerVictor Campos2019-10-182-0/+29
| | | | | | | | | | | | | | | | | | Summary: The PMMIR_EL1 register is present in Armv8.4 with PMU extension. This patch adds support for it. Reviewers: t.p.northover, dnsampaio Reviewed By: dnsampaio Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68940 llvm-svn: 375228
* [lit] Fix internal diff's --strip-trailing-cr and use itJoel E. Denny2019-10-162-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Using GNU diff, `--strip-trailing-cr` removes a `\r` appearing before a `\n` at the end of a line. Without this patch, lit's internal diff only removes `\r` if it appears as the last character. That seems useless. This patch fixes that. This patch also adds `--strip-trailing-cr` to some tests that fail on Windows bots when D68664 is applied. Based on what I see in the bot logs, I think the following is happening. In each test there, lit diff is comparing a file with `\r\n` line endings to a file with `\n` line endings. Without D68664, lit diff reads those files in text mode, which in Windows causes `\r\n` to be replaced with `\n`. However, with D68664, lit diff reads the files in binary mode instead and thus reports that every line is different, just as GNU diff does (at least under Ubuntu). Adding `--strip-trailing-cr` to those tests restores the previous behavior while permitting the behavior of lit diff to be more like GNU diff. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D68839 llvm-svn: 375020
* [AArch64,Assembler] Compiler support for ID_MMFR5_EL1Mark Murray2019-10-163-0/+8
| | | | | | | | | | | | Summary: Add read-only system register ID_MMFR5_EL1 and unit tests. Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69039 llvm-svn: 375010
* Added support for "#pragma clang section relro=<name>"Dmitry Mikulin2019-10-151-0/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D68806 llvm-svn: 374934
OpenPOWER on IntegriCloud