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* [mips] Fix lowering load/store instruction in PIC caseSimon Atanasyan2019-08-012-0/+112
| | | | | | | | | | | | | | | | | | | | | If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
* [RISCV] Add Custom Parser for Atomic Memory OperandsSam Elliott2019-08-015-6/+588
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC Accepts both (reg) and 0(reg) for atomic instruction memory operands. These instructions do not allow for an offset in their encoding, so in the latter case, the 0 is silently dropped. Due to how we have structured the RISCVAsmParser, the easiest way to add support for parsing this offset is to add a custom AsmOperand and parser. This parser drops all the parens, and just keeps the register. This commit also adds a custom printer for these operands, which matches the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: s.egerton, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65205 llvm-svn: 367553
* [ARM] Reject CSEL instructions with invalid operandsMikhail Maltsev2019-07-312-13/+30
| | | | | | | | | | | | | | | | | | | | Summary: According to the Armv8.1-M manual CSEL, CSINC, CSINV and CSNEG are "constrained unpredictable" when SP is used as the source register Rn. The assembler should diagnose this case. Reviewers: momchil.velikov, dmgreen, ostannard, simon_tatham, t.p.northover Reviewed By: ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65505 llvm-svn: 367433
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-313-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | Re-commit r366322 after some fixes TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Differential Revision: https://reviews.llvm.org/D64416 Patch by Javed Absar and Momchil Velikov llvm-svn: 367428
* [RISCV] Attempt to make rv{32,64}i-aliases-invalid.s less flakySam Elliott2019-07-302-6/+6
| | | | | | | | | | | These tests have been disabled on Linux and Windows due to failing there. I think that could be down to a race condition between stdout and stderr, so I have disabled output to stdout. For the moment, only re-enable on linux, because I don't have a windows machine to test on. llvm-svn: 367311
* Mark test/MC/RISCV/rv{32,64}i-aliases-invalid.s unsupported also on WindowsHans Wennborg2019-07-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because they fail there too. FAIL: LLVM :: MC/RISCV/rv32i-aliases-invalid.s (24397 of 32659) ******************** TEST 'LLVM :: MC/RISCV/rv32i-aliases-invalid.s' FAILED ******************** Script: -- : 'RUN: at line 2'; not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s -triple=riscv32 -riscv-no-aliases 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s : 'RUN: at line 3'; not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s -triple=riscv32 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s -- Exit Code: 1 Command Output (stdout): -- $ ":" "RUN: at line 2" $ "not" "c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s" "-triple=riscv32" "-riscv-no-aliases" $ "c:\src\llvm.monorepo\build.release2\bin\filecheck.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s" C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s:10:21: error: CHECK: expected string not found in input li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] ^ <stdin>:5:1: note: scanning from here li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] ^ <stdin>:5:1: note: with "@LINE" equal to "10" li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] ^ <stdin>:5:38: note: possible intended match here li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] ^ error: command failed with exit status: 1 -- -- ******************** Testing: 0 .. 10.. 20.. 30.. 40.. 50.. 60.. 70 FAIL: LLVM :: MC/RISCV/rv64i-aliases-invalid.s (24416 of 32659) ******************** TEST 'LLVM :: MC/RISCV/rv64i-aliases-invalid.s' FAILED ******************** Script: -- : 'RUN: at line 2'; not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s -triple=riscv64 -riscv-no-aliases 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s : 'RUN: at line 3'; not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s -triple=riscv64 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s -- Exit Code: 1 Command Output (stdout): -- $ ":" "RUN: at line 2" $ "not" "c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s" "-triple=riscv64" "-riscv-no-aliases" $ "c:\src\llvm.monorepo\build.release2\bin\filecheck.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s" C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s:6:21: error: CHECK: expected string not found in input li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer ^ <stdin>:2:1: note: scanning from here li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand ^ <stdin>:2:1: note: with "@LINE" equal to "6" li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand ^ <stdin>:13:67: note: possible intended match here C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s:12:13: error: immediate must be an integer in the range [0, 63] ^ error: command failed with exit status: 1 llvm-svn: 367215
* [mips] Add (dis)assembler tests for beqzl and bnezl instructions. NFCSimon Atanasyan2019-07-273-0/+6
| | | | llvm-svn: 367168
* [AArch64][SVE2] Rename bitperm feature to sve2-bitpermCullen Rhodes2019-07-2612-39/+39
| | | | | | | | | | | | | | | | Summary: The bitperm feature flag is now prefixed with SVE2, as it is for all other SVE2 extensions Patch by Maciej Gabka. Reviewers: sdesmalen, rovka, chill, SjoerdMeijer, rengolin Reviewed By: SjoerdMeijer, rengolin Differential Revision: https://reviews.llvm.org/D65327 llvm-svn: 367124
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-265-0/+148
| | | | | | | | | | | | | | | | | | | | Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
* [AArch64][SVE] Allow explicit size specifier for predicate operandMomchil Velikov2019-07-256-29/+137
| | | | | | | | | | | | | ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-257-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1. Neoverse E1 and Cortex-A65(&AE) only implement the AArch64 state of the Arm architecture. Neoverse N1 implements both AArch32 and AArch64. Cortex-A65: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65 Cortex-A65AE: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae Neoverse E1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1 Neoverse N1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 Patch by Diogo Sampaio and Pablo Barrio Reviewers: samparker, LukeCheeseman, sbaranga, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64406 llvm-svn: 367007
* [AMDGPU][MC][GFX10] Enabled GFX10 assembly with arbitrary wavesize assumed ↵Dmitry Preobrazhensky2019-07-241-0/+238
| | | | | | | | | | by the code Reviewers: rampitec, arsenm Differential Revision: https://reviews.llvm.org/D65216 llvm-svn: 366921
* [AMDGPU] Add all vgpr classes to asm parserStanislav Mekhanoshin2019-07-242-2/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D65158 llvm-svn: 366917
* [RISCV][NFC] Correct RUN in rvi-pseudos-invalid.sSam Elliott2019-07-231-1/+1
| | | | | | This test should test both riscv32 and riscv64. llvm-svn: 366825
* Revert [RISCV] Re-enable rv32i-aliases-invalid.s testSam Elliott2019-07-231-0/+1
| | | | | | This reverts r366797 (git commit 53f9fec8e8b58f5a904bbfb4a1d648cde65aa860) llvm-svn: 366806
* [RISCV] Re-enable rv32i-aliases-invalid.s testSam Elliott2019-07-231-1/+0
| | | | | | | | | We were getting test failures on some builders, which pointed to @LINE being an undefined variable. I think that these failures should have been fixed by https://reviews.llvm.org/rL366434, so I'm re-enabling the test. llvm-svn: 366797
* Revert "Reland [ELF] Loose a condition for relocation with a symbol"Vlad Tsyrklevich2019-07-225-9/+15
| | | | | | | This reverts commit r366686 as it appears to be causing buildbot failures on sanitizer-x86_64-linux-android and sanitizer-x86_64-linux. llvm-svn: 366708
* Reland [ELF] Loose a condition for relocation with a symbolNikola Prica2019-07-225-15/+9
| | | | | | | | | | | | | | | | | | | This patch was not the reason of the buildbot failure. Deleted code was introduced as a work around for a bug in the gold linker (http://sourceware.org/PR16794). Test case that was given as a reason for this part of code, the one on previous link, now works for the gold. This condition is too strict and when a code is compiled with debug info it forces generation of numerous relocations with symbol for architectures that do not have relocation addend. Reviewers: arsenm, espindola Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D64327 llvm-svn: 366686
* [RISCV] Disable tests failing on buildbots.Matt Morehouse2019-07-192-0/+2
| | | | | | r366399 enabled a couple tests that are failing on a few buildbots. llvm-svn: 366599
* [AMDGPU][MC] Corrected parsing of branch offsetsDmitry Preobrazhensky2019-07-194-3/+40
| | | | | | | | | | See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D64629 llvm-svn: 366571
* [ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev2019-07-192-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: According to the new Armv8-M specification https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf the instructions SQRSHRL and UQRSHLL now have an additional immediate operand <saturate>. The new assembly syntax is: SQRSHRL<c> RdaLo, RdaHi, #<saturate>, Rm UQRSHLL<c> RdaLo, RdaHi, #<saturate>, Rm where <saturate> can be either 64 (the existing behavior) or 48, in that case the result is saturated to 48 bits. The new operand is encoded as follows: #64 Encoded as sat = 0 #48 Encoded as sat = 1 sat is bit 7 of the instruction bit pattern. This patch adds a new assembler operand class MveSaturateOperand which implements parsing and encoding. Decoding is implemented in DecodeMVEOverlappingLongShift. Reviewers: ostannard, simon_tatham, t.p.northover, samparker, dmgreen, SjoerdMeijer Reviewed By: simon_tatham Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64810 llvm-svn: 366555
* [DebugInfo] Some fields do not need relocations even relax is enabled.Hsiangkai Wang2019-07-191-6/+3
| | | | | | | | | | | | | | | | In debug frame information, some fields, e.g., Length in CIE/FDE and Offset in FDE are attributes to describe the structure of CIE/FDE. They are not related to the relaxed code. However, these attributes are symbol differences. So, in current design, these attributes will be filled as zero and LLVM generates relocations for them. We only need to generate relocations for symbols in executable sections. So, if the symbols are not located in executable sections, we still evaluate their values under relaxation. Differential Revision: https://reviews.llvm.org/D61584 llvm-svn: 366531
* MC: AArch64: Add support for prel_g* relocation specifiers.Peter Collingbourne2019-07-181-5/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D64683 llvm-svn: 366462
* AArch64: Unify relocation restrictions between MOVK/MOVN/MOVZ.Peter Collingbourne2019-07-181-54/+0
| | | | | | | | | | | | | | | | | | | | | | | There doesn't seem to be a practical reason for these instructions to have different restrictions on the types of relocations that they may be used with, notwithstanding the language in the ELF AArch64 spec that implies that specific relocations are meant to be used with specific instructions. For example, we currently forbid the first instruction in the following sequence, despite it currently being used by clang to generate a global reference under -mcmodel=large: movz x0, #:abs_g0_nc:foo movk x0, #:abs_g1_nc:foo movk x0, #:abs_g2_nc:foo movk x0, #:abs_g3:foo Therefore, allow MOVK/MOVN/MOVZ to accept the union of the set of relocations that they currently accept individually. Differential Revision: https://reviews.llvm.org/D64466 llvm-svn: 366461
* Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang2019-07-181-3/+6
| | | | | | This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. llvm-svn: 366444
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-181-6/+3
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366442
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-173-90/+0
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [RISCV][NFC] Add tests that capture current encodings for DWARF EHAlex Bradbury2019-07-171-0/+31
| | | | | | | Items which are known to be wrong/different vs GCC are marked as TODO and will be address in follow-up patches. llvm-svn: 366326
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-173-0/+90
| | | | | | | | | | | | | | | | | | | | | | | TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Patch by Javed Absar and Momchil Velikov Differential Revision: https://reviews.llvm.org/D64416 llvm-svn: 366322
* [mips] Implement .cplocal directiveSimon Atanasyan2019-07-172-0/+65
| | | | | | | | | | | | | | This directive forces to use the alternate register for context pointer. For example, this code: .cplocal $4 jal foo expands to: ld $25, %call16(foo)($4) jalr $25 Differential Revision: https://reviews.llvm.org/D64743 llvm-svn: 366300
* [RISCV] Match GNU tools canonical JALR and add aliasesAlex Bradbury2019-07-165-26/+38
| | | | | | | | | | | | The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
* [RISCV] Avoid overflow when determining number of nops for code alignAlex Bradbury2019-07-161-0/+7
| | | | | | | | | | | | RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign() assumed that the align specified would be greater than or equal to the minimum nop length, but that is not always the case - for example if a user specifies ".align 0" in assembly. Differential Revision: https://reviews.llvm.org/D63274 Patch by Edward Jones. llvm-svn: 366176
* [WebAssembly] Rename except_ref type to exnrefHeejin Ahn2019-07-153-5/+5
| | | | | | | | | | | | | | | | | | | Summary: We agreed to rename `except_ref` to `exnref` for consistency with other reference types in https://github.com/WebAssembly/exception-handling/issues/79. This also renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order to use the file for other reference types in future. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64703 llvm-svn: 366145
* [WebAssembly] Assembler: support special floats: infinity / nanWouter van Oortmerssen2019-07-151-0/+4
| | | | | | | | | | | | | | | | | Summary: These are emitted as identifiers by the InstPrinter, so we should parse them as such. These could potentially clash with symbols of the same name, but that is out of our (the WebAssembly backend) control. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64770 llvm-svn: 366139
* [mips] Print BEQZL and BNEZL pseudo instructionsSimon Atanasyan2019-07-153-26/+26
| | | | | | One of the reasons - to be compatible with GNU tools. llvm-svn: 366133
* [WebAssembly] Assembler: recognize .init_array as data section.Wouter van Oortmerssen2019-07-151-3/+12
| | | | | | | | | | | | Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64602 llvm-svn: 366104
* [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL messageDmitry Preobrazhensky2019-07-152-1/+28
| | | | | | | | Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D64729 llvm-svn: 366071
* [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructionsDmitry Preobrazhensky2019-07-1510-140/+140
| | | | | | | | | | See bug 42599: https://bugs.llvm.org/show_bug.cgi?id=42599 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D64716 llvm-svn: 366067
* [macCatalyst] Use macCatalyst pretty name in .build_version darwinAlex Lorenz2019-07-121-2/+2
| | | | | | | | | assembly command 'macCatalyst' is more readable than 'maccatalyst'. I renamed the objdump output, but the assembly should match it as well. llvm-svn: 365964
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-124-0/+4017
| | | | | | | | | | | | | | | | | | This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
* [RISCV] Allow parsing dot '.' in assemblySam Elliott2019-07-123-0/+12
| | | | | | | | | | | | | | | | | | | | | Summary: Useful for jumps, such as `j .`. I am not sure who should review this. Do not hesitate to change the reviewers if needed. Reviewers: asb, jrtc27, lenary Reviewed By: lenary Subscribers: MaskRay, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63669 Patch by John LLVM (JohnLLVM) llvm-svn: 365881
* [WebAssembly] Assembler: support negative float constants.Wouter van Oortmerssen2019-07-111-0/+2
| | | | | | | | | | | | Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64367 llvm-svn: 365802
* [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.Simon Tatham2019-07-112-37/+38
| | | | | | | | | | | | | | | | | | | | The VQDMLAH.U8, VQDMLAH.U16 and VQDMLAH.U32 instructions don't actually exist: the Armv8.1-M architecture spec only lists signed forms of that instruction. The unsigned ones were added in error: they existed in an early draft of the spec, but they were removed before the public version, and we missed that particular spec change. Also affects the variant forms VQDMLASH, VQRDMLAH and VQRDMLASH. Reviewers: miyuki Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64502 llvm-svn: 365747
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-112-0/+213
| | | | | | Differential Revision: https://reviews.llvm.org/D64435 llvm-svn: 365717
* [AMDGPU] gfx908 dot instruction supportStanislav Mekhanoshin2019-07-114-170/+932
| | | | | | Differential Revision: https://reviews.llvm.org/D64431 llvm-svn: 365715
* Revert "[ELF] Loose a condition for relocation with a symbol"Nikola Prica2019-07-105-9/+15
| | | | | | | | This reverts commit 8507eca1647118e73435b0ce1de8a1952a021d01. Reveting due to some suspicious failurse in santizer-x86_64-linux. llvm-svn: 365685
* MC: AArch64: Add support for pg_hi21_nc relocation specifier.Peter Collingbourne2019-07-101-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D64455 llvm-svn: 365661
* [ELF] Loose a condition for relocation with a symbolNikola Prica2019-07-105-15/+9
| | | | | | | | | | | | | | | | | Deleted code was introduced as a work around for a bug in the gold linker (http://sourceware.org/PR16794). Test case that was given as a reason for this part of code, the one on previous link, now works for the gold. This condition is too strict and when a code is compiled with debug info it forces generation of numerous relocations with symbol for architectures that do not have relocation addend. Reviewers: arsenm, espindola Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D64327 llvm-svn: 365618
* [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is presentMikhail Maltsev2019-07-101-0/+32
| | | | | | | | | | | | | | | | | | | | Summary: Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to these. Patch by Momchil Velikov. Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen Reviewed By: dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64413 llvm-svn: 365604
* [AMDGPU] gfx908 v_pk_fmac_f16 supportStanislav Mekhanoshin2019-07-092-0/+92
| | | | | | Differential Revision: https://reviews.llvm.org/D64433 llvm-svn: 365573
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