summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC
Commit message (Collapse)AuthorAgeFilesLines
...
* [mips] Fix decoding of microMIPS JALX instructionSimon Atanasyan2019-09-092-0/+2
| | | | | | | | | | | | | microMIPS jump and link exchange instruction stores a target in a 26-bits field. Despite other microMIPS JAL instructions these bits are target address shifted right 2 bits [1]. The patch fixes the JALX instruction decoding and uses 2-bit shift. [1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set Differential Revision: https://reviews.llvm.org/D67320 llvm-svn: 371428
* [ARM] Remove some spurious MVE reduction instructions.Simon Tatham2019-09-092-1/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The family of 'dual-accumulating' vector multiply-add instructions (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and unsigned integer types, and they all have an 'exchange' variant (with an X in the name) that modifies which pairs of vector lanes in the two inputs are multiplied together. But there's a clause in the spec that says that the X variants //don't// operate on unsigned integer types, only signed. You can have X, or unsigned, or neither, but not both. We didn't notice that clause when we implemented the MC support for these instructions, so LLVM believes that things like VMLADAVX.U8 do exist, contradicting the spec. Here I fix that by conditioning them out in Tablegen. In order to do that, I've reversed the nesting order of the Tablegen multiclasses for those instructions. Previously, the innermost multiclass generated the X and not-X variants, and the one outside that generated the A and not-A variants. Now X is done by the outer multiclass, which allows me to bypass that one when I only want the two not-X variants. Changing the multiclass nesting order also changes the names of the instruction ids unless I make a special effort not to. I decided that while I was changing them anyway I'd make them look nicer; so now the instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead of cumbersome _noacc_noexch suffixes. The corresponding multiply-subtract instructions are unaffected. Those don't accept unsigned types at all, either in the spec or in LLVM. Reviewers: ostannard, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67214 llvm-svn: 371405
* [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard2019-09-091-0/+42
| | | | | | | | | | Specify the Unpredictable bits, and return softfails when appropriate. Patch by Mark Murray! Differential revision: https://reviews.llvm.org/D66939 llvm-svn: 371374
* [ELF][MC] Set types of aliases of IFunc to STT_GNU_IFUNCFangrui Song2019-09-071-0/+32
| | | | | | | | | | | | | | | | | | ``` .type foo,@gnu_indirect_function .set foo,foo_resolver .set foo2,foo .set foo3,foo2 ``` The types of foo2 and foo3 should be STT_GNU_IFUNC, but we currently resolve them to the type of foo_resolver. This patch fixes it. Differential Revision: https://reviews.llvm.org/D67206 Patch by Senran Zhang llvm-svn: 371312
* [MC] Pass through .code16/32/64 and .syntax unified for COFFReid Kleckner2019-09-031-0/+21
| | | | | | | | | | | | | | These flags should simply be passed through to the target, which will do the right thing. Add an MC/X86 test that uses these directives with the three primary object file formats and shows that they disassemble the same everywhere. There is a missing test for .code32 on Windows ARM, since I'm not sure exactly how to construct one. Fixes PR43203 llvm-svn: 370805
* [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operandsDavid Green2019-09-031-0/+12
| | | | | | | | | | | | | | The code here seems to date back to r134705, when tablegen lowering was first being added. I don't believe that we need to include CPSR implicit operands on the MCInst. This now works more like other backends (like AArch64), where all implicit registers are skipped. This allows the AliasInst for CSEL's to match correctly, as can be seen in the test changes. Differential revision: https://reviews.llvm.org/D66703 llvm-svn: 370745
* [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodingsOliver Stannard2019-09-031-0/+178
| | | | | | | | | | | | | | | | Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set. Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g. Fill in the "should-be-(0)" bits. Designate the Unpredictable{} bits for both VMRS and VMSR. Patch by Mark Murray! Differential revision: https://reviews.llvm.org/D66938 llvm-svn: 370729
* [AMDGPU][MC][GFX10] Corrected constant bus checks to exclude nullDmitry Preobrazhensky2019-09-021-0/+6
| | | | | | | | | | See AMD SWDEV-157286 Reviewers: atamazov, arsenm Differential Revision: https://reviews.llvm.org/D65229 llvm-svn: 370665
* [AMDGPU][MC][GFX10] Enabled null with 64-bit operandsDmitry Preobrazhensky2019-09-021-0/+8
| | | | | | | | | | See Bug 42745: https://bugs.llvm.org/show_bug.cgi?id=42745 Reviewers: atamazov, arsenm https://reviews.llvm.org/D65231 llvm-svn: 370660
* [AMDGPU][MC][GFX10] Corrected constant bus limit for 64-bit shift instructionsDmitry Preobrazhensky2019-09-022-5/+13
| | | | | | | | | | See bug 42744: https://bugs.llvm.org/show_bug.cgi?id=42744 Reviewers: atamazov, arsenm Differential Revision: https://reviews.llvm.org/D65228 llvm-svn: 370652
* [WebAssembly] Add SIMD QFMA/QFMSThomas Lively2019-08-311-0/+12
| | | | | | | | | | | | | | | | | | | Summary: Adds clang builtins and LLVM intrinsics for these experimental instructions. They are not implemented in engines yet, but that is ok because the user must opt into using them by calling the builtins. Reviewers: aheejin, dschuff Reviewed By: aheejin Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67020 llvm-svn: 370556
* [MC] Avoid crashes from improperly nested or wrong target .seh_handlerdata ↵Reid Kleckner2019-08-301-0/+4
| | | | | | directives llvm-svn: 370540
* [X86] Print register names in .seh_* directivesReid Kleckner2019-08-305-23/+47
| | | | | | | | | | Also improve assembler parser register validation for .seh_ directives. This requires moving X86-specific seh directive handling into the x86 backend, which addresses some assembler FIXMEs. Differential Revision: https://reviews.llvm.org/D66625 llvm-svn: 370533
* [WebAssembly] Make __attribute__((used)) not imply export.Dan Gohman2019-08-291-2/+2
| | | | | | | | | | Add an WASM_SYMBOL_NO_STRIP flag, so that __attribute__((used)) doesn't need to imply exporting. When targeting Emscripten, have WASM_SYMBOL_NO_STRIP imply exporting. Differential Revision: https://reviews.llvm.org/D62542 llvm-svn: 370415
* [PowerPC] Support extended mnemonics mffprwz etc.Jinsong Ji2019-08-292-12/+73
| | | | | | | | | | | | | | | | | | | | | | Summary: Reported in https://github.com/opencv/opencv/issues/15413. We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions eg: mffprd,mtfprd etc. We only support one of them, this patch add the others. Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc Reviewed By: hfinkel Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66963 llvm-svn: 370411
* Allow '@' to appear in x86 mingw symbolsReid Kleckner2019-08-291-0/+19
| | | | | | | | | | | | | | | | | Summary: There is no reason to differ in assembler behavior here between -msvc and -gnu targets. Without this setting, the text after the '@' is interpreted as a symbol variable, like foo@IMGREL. Reviewers: mstorsjo Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66974 llvm-svn: 370408
* [mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instructionSimon Atanasyan2019-08-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | When a "base" in the `lw/sw $reg1, symbol($reg2)` instruction is a register and generated code is position independent, backend does not add the "base" value to the symbol address. ``` lw $reg1, %got(symbol)($gp) lw/sw $reg1, 0($reg1) ``` This patch fixes the bug and adds the missed `addu` instruction by passing `BaseReg` into the `loadAndAddSymbolAddress` routine and handles the case when the `BaseReg` is the zero register to escape redundant `move reg, reg` instruction: ``` lw $reg1, %got(symbol)($gp) addu $reg1, $reg1, $reg2 lw/sw $reg1, 0($reg1) ``` Differential Revision: https://reviews.llvm.org/D66894 llvm-svn: 370353
* [WebAssembly] Add atomic.fence instructionHeejin Ahn2019-08-281-0/+3
| | | | | | | | | | | | | | | | | | | Summary: This adds `atomic.fence` instruction: https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#fence-operator And we now emit the new `atomic.fence` instruction for multithread fences, rather than the prevous `atomic.rmw` hack. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, tlively, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66794 llvm-svn: 370272
* [AMDGPU] Fix bug when calculating user_spgr_count for Code Object V3 assemblerScott Linder2019-08-281-1/+28
| | | | | | | | Stop counting explicitly disabled user_spgr's in the user_sgpr_count field of the kernel descriptor. Differential Revision: https://reviews.llvm.org/D66900 llvm-svn: 370250
* [AMDGPU] Check for immediate SrcC in mfma in AsmParserStanislav Mekhanoshin2019-08-232-480/+477
| | | | | | Differential Revision: https://reviews.llvm.org/D66674 llvm-svn: 369819
* Revert r369233.Manoj Gupta2019-08-235-76/+153
| | | | | | | | This breaks building of some projects like libfuse and alsa-lib that now fail when linking. Error details in PR43092. llvm-svn: 369790
* [mips] Reduce number of instructions used for loading a global symbol's valueSimon Atanasyan2019-08-232-34/+28
| | | | | | | | | | | | | | | | | | | | | | Now `lw/sw $reg, sym+offset` pseudo instructions for global symbol `sym` are lowering into the following three instructions. ``` lw $reg, %got(symbol)($gp) addiu $reg, $reg, offset lw/sw $reg, 0($reg) ``` It's possible to reduce the number of instructions by taking the offset in account in the final `lw/sw` command. This patch implements that optimization. ``` lw $reg, %got(symbol)($gp) lw/sw $reg, offset($reg) ``` Differential Revision: https://reviews.llvm.org/D66553 llvm-svn: 369756
* [mips] Do not include offset into `%got` expression for global symbolsSimon Atanasyan2019-08-232-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | Now pseudo instruction `la $6, symbol+8($6)` is expanding into the following chain of commands: ``` lw $1, %got(symbol+8)($gp) addiu $1, $1, 8 addu $6, $1, $6 ``` This is incorrect. When a linker handles the `R_MIPS_GOT16` relocation, it does not expect to get any addend and breaks on assertion. Otherwise it has to create new GOT entry for each unique "sym + offset" pair. Offset for a global symbol should be added to result of loading GOT entry by a separate `add` command. The patch fixes the problem by stripping off an offset from the expression passed to the `%got`. That's interesting that even current code inserts a separate `add` command. Differential Revision: https://reviews.llvm.org/D66552 llvm-svn: 369755
* [MachO][TLOF] Use hasLocalLinkage to determine if indirect symbol is localFrancis Visoiu Mistrih2019-08-221-5/+32
| | | | | | | | | | | | | | | | | | | | | Local symbols in the indirect symbol table contain the value `INDIRECT_SYMBOL_LOCAL` and the corresponding __pointers entry must contain the address of the target. In r349060, I added support for local symbols in the indirect symbol table, which was checking if the symbol `isDefined` && `!isExternal` to determine if the symbol is local or not. It turns out that `isDefined` will return false if the user of the symbol comes before its definition, and we'll again generate .long 0 which will be the symbol at the adress 0x0. Instead of doing that, use GlobalValue::hasLocalLinkage() to check if the symbol is local. Differential Revision: https://reviews.llvm.org/D66563 llvm-svn: 369671
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-214-8/+106
| | | | | | | | | The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints. Differential Revision: https://reviews.llvm.org/D62592 llvm-svn: 369528
* [AArch64] Update MTE system register encodingsLuke Cheeseman2019-08-212-30/+30
| | | | | | | | | | The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3 and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6 as per https://developer.arm.com/docs/ddi0487/latest. Differential Revision: https://reviews.llvm.org/D65442 llvm-svn: 369505
* [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for ↵Alex Bradbury2019-08-201-7/+1
| | | | | | | | | | | | | | | | | | the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375
* [WebAssembly][MC] Simplify WasmObjectWriter::recordRelocation. NFC.Sam Clegg2019-08-201-0/+32
| | | | | | | | | | | | WebAssembly doesn't support PC relative relocation or relocation expressions that can't be reduced to single symbol. The only support for we have for fixups involving two symbols are when both symbols are defined and withing the same section. In this case evaluateFixup will already have evaluated to the expression before calling recordRelocation. llvm-svn: 369317
* [WebAssembly][MC] Allow empty assembly functionsSam Clegg2019-08-191-0/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D66434 llvm-svn: 369292
* [RISCV] Don't force absolute FK_Data_X fixups to relocsAlex Bradbury2019-08-192-3/+21
| | | | | | | | | | | | The current behavior of shouldForceRelocation forces relocations for the majority of fixups when relaxation is enabled. This makes sense for fixups which incorporate symbols but is unnecessary for simple data fixups where the fixup target is already resolved to an absolute value. Differential Revision: https://reviews.llvm.org/D63404 Patch by Edward Jones. llvm-svn: 369257
* [MC] Delete unnecessary diagnostic: "No relocation available to represent ↵Fangrui Song2019-08-194-5/+5
| | | | | | | | | | | | | | | | | | | | this relative expression" Replace - error: No relocation available to represent this relative expression with + error: symbol 'undef' can not be undefined in a subtraction expression or + error: Cannot represent a difference across sections Keep !IsPcRel as an assertion after the two diagnostic checks are done. llvm-svn: 369239
* [MC] Don't emit .symver redirected symbols to the symbol tableFangrui Song2019-08-195-153/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GNU as keeps the original symbol in the symbol table for defined @ and @@, but suppresses it in other cases (@@@ or undefined). The original symbol is usually undesired: In a shared object, the original symbol can be localized with a version script, but it is hard to remove/localize in an archive: 1) a post-processing step removes the undesired original symbol 2) consumers (executable) of the archive are built with the version script Moreover, it can cause linker issues like binutils PR/18703 if the original symbol name and the base name of the versioned symbol is the same (both ld.bfd and gold have some code to work around defined @ and @@). In lld, if it sees f and f@v1: --version-script =(printf 'v1 {};') => f and f@v1 --version-script =(printf 'v1 { f; };') => f@v1 and f@@v1 It can be argued that @@@ added on 2000-11-13 corrected the @ and @@ mistake. This patch catches some more multiple version errors (defined @ and @@), and consistently suppress the original symbol. This addresses all the problems listed above. If the user wants other aliases to the versioned symbol, they can copy the original symbol to other symbol names with .set directive, e.g. .symver f, f@v1 # emit f@v1 but not f into .symtab .set f_impl, f # emit f_impl into .symtab llvm-svn: 369233
* [RISCV] Allow parsing of bare symbols with offsetsLewis Revill2019-08-161-62/+67
| | | | | | | | | This patch allows symbols followed by an expression for an offset to be parsed as bare symbols. Differential Revision: https://reviews.llvm.org/D57332 llvm-svn: 369097
* [llvm-readobj][MachO] Fix section type printingSeiya Nuta2019-08-1549-191/+191
| | | | | | | | | | | | | | | | | | | Summary: Currently, llvm-readobj mistakenly decodes section type as section attribute. This patch fixes the bug and affected tests. Reviewers: JDevlieghere, jhenderson, rupprecht, alexshap, echristo Reviewed By: jhenderson, rupprecht, alexshap, echristo Subscribers: javed.absar, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66075 llvm-svn: 368974
* [ARM] Fix detection of duplicates when parsing reg list operandsMomchil Velikov2019-08-131-0/+66
| | | | | | Differential Revision: https://reviews.llvm.org/D65957 llvm-svn: 368712
* [ARM] Fix encoding of APSR in CLRM instructionMomchil Velikov2019-08-131-3/+6
| | | | | | | | | The APSR is encoded by setting bit 15 in the register list of the CLRM instruction (cf. https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf). Differential Revision: https://reviews.llvm.org/D65873 llvm-svn: 368711
* [X86] Improve the diagnostic for larger than 4-bit immediate for ↵Craig Topper2019-08-101-2/+2
| | | | | | vpermil2pd/ps. Only allow MCConstantExprs. llvm-svn: 368505
* [llvm-mc] Add reportWarning() to MCContextBrian Cain2019-08-081-0/+19
| | | | | | | Adding reportWarning() to MCContext, so that it can be used from the Hexagon assembler backend. llvm-svn: 368327
* [Mips] Instruction `sc` now accepts symbol as an argumentSimon Atanasyan2019-08-071-0/+74
| | | | | | | | | | | | | Function MipsAsmParser::expandMemInst() did not properly handle instruction `sc` with a symbol as an argument because first argument would be counted twice. We add additional checks and handle this case separately. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D64252 llvm-svn: 368160
* [X86] Allow any 8-bit immediate to be used with bt/btc/btr/bts memory aliases.Craig Topper2019-08-071-0/+4
| | | | | | | | We have aliases that disambiguate memory forms of bt/btc/btr/bts without suffixes to the 32-bit form. These aliases should have been updated when the instructions were updated in r356413. llvm-svn: 368127
* [X86] Limit vpermil2pd/vpermil2ps immediates to 4 bits in the assembly parser.Craig Topper2019-08-071-0/+4
| | | | | | | | | | The upper 4 bits of the immediate byte are used to encode a register. We need to limit the explicit immediate to fit in the remaining 4 bits. Fixes PR42899. llvm-svn: 368123
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-1/+1
| | | | | | | | | | | | | | | | Summary: During fdiv32 lowering use S_DENORM_MODE to select denorm mode in gfx10. Reviewers: arsenm, rampitec Reviewed By: arsenm, rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65620 llvm-svn: 367969
* Revert "Try to fix failing AMDGPU disasm test, both Lin/Win agree this is 0 ↵Dmitri Gribenko2019-08-051-1/+1
| | | | | | | | not 0x0" This reverts commit r367907, it broke the test. llvm-svn: 367909
* Try to fix failing AMDGPU disasm test, both Lin/Win agree this is 0 not 0x0Reid Kleckner2019-08-051-1/+1
| | | | llvm-svn: 367907
* Changing representation of .cv_def_range directives in Codeview debug info ↵Nilanjana Basu2019-08-054-5/+100
| | | | | | assembly format for better readability llvm-svn: 367867
* Revert "Changing representation of .cv_def_range directives in Codeview ↵Nilanjana Basu2019-08-053-5/+5
| | | | | | | | debug info assembly format for better readability" This reverts commit a885afa9fa8cab3b34f1ddf3d21535f88b662881. llvm-svn: 367861
* Changing representation of .cv_def_range directives in Codeview debug info ↵Nilanjana Basu2019-08-053-5/+5
| | | | | | assembly format for better readability llvm-svn: 367850
* Temporarily Revert "Changing representation of cv_def_range directives in ↵Eric Christopher2019-08-024-100/+5
| | | | | | | | | | Codeview debug info assembly format for better readability" This is breaking bots and the author asked me to revert. This reverts commit 367704. llvm-svn: 367707
* Changing representation of cv_def_range directives in Codeview debug info ↵Nilanjana Basu2019-08-024-5/+100
| | | | | | assembly format for better readability llvm-svn: 367704
* [WebAssembly] Assembler/InstPrinter: support call_indirect type index.Wouter van Oortmerssen2019-08-013-4/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A TYPE_INDEX operand (as used by call_indirect) used to be represented by the InstPrinter as a symbol (e.g. .Ltype_index0@TYPE_INDEX) which was a bit of a mismatch with the WasmObjectWriter which expects an unnamed symbol, to receive the signature from and then turn into a reloc. There was really no good way to round-trip this information. An earlier version of this patch tried to attach the signature information using a .functype, but that ran into trouble when the symbol was re-emitted without a name. Removing the name was a giant hack also. The current version changes the assembly syntax to have an inline signature spec for TYPEINDEX operands that is always unnamed, which is much more elegant both in syntax and in implementation (as now the assembler is able to follow the same path as the regular backend) Reviewers: sbc100, dschuff, aheejin, jgravelle-google, sunfish, tlively Subscribers: arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64758 llvm-svn: 367590
OpenPOWER on IntegriCloud