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* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-074-0/+78
| | | | | | | | | | extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
* [RISCV] Add missed tests for RV64D MC layer supportAlex Bradbury2017-12-072-0/+60
| | | | | | Add tests missed in r320029. llvm-svn: 320031
* [RISCV] MC layer support for the standard RV64F instruction set extensionAlex Bradbury2017-12-073-0/+48
| | | | llvm-svn: 320028
* [RISCV] MC layer support for the standard RV64A instruction set extensionAlex Bradbury2017-12-073-0/+206
| | | | llvm-svn: 320027
* [RISCV] MC layer support for the standard RV64M instruction set extensionAlex Bradbury2017-12-072-0/+29
| | | | llvm-svn: 320026
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-073-2/+120
| | | | llvm-svn: 320024
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-073-0/+183
| | | | | | | | | | | As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-073-0/+197
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [X86][FMA][FMA4]: Adding full coverage of MC encoding for the FMA, FMA4 isa ↵Gadi Haber2017-12-072-0/+8068
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the FMA and FMA4 ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets starting revision https://reviews.llvm.org/D39952 Reviewers: craig.topper, RKSimon, zvi Differential Revision: https://reviews.llvm.org/D40880 Change-Id: Ie39c0edce69ad647076b3d4e816948b2b6e1a9e4 llvm-svn: 320016
* [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>Gadi Haber2017-12-072-0/+3236
| | | | | | | | | | | | | NFC. Currently, not all the X86 ISA Sets are covered by the MC regressions tests for X86. A full coverage needs to be added for each ISA set and for both 32bit and 64bit instructions + registers. This patch includes MC assembly tests for the X87 32bit and 64bit. Reviewers: craigt, RKSimon, zvi Differential Revision: https://reviews.llvm.org/D39952 Change-Id: I55e1719c09a70644a6a4073c720cb5341c80fee9 llvm-svn: 320015
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-071-0/+61
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* Revert "[WebAssembly] Import the linear memory and function table."Sam Clegg2017-12-078-39/+32
| | | | | | | | | We need to a little time to prepare and lld-side change that supports this. Original change: https://reviews.llvm.org/D40875 llvm-svn: 320003
* [WebAssembly] section kind can be codeSam Clegg2017-12-071-0/+9
| | | | | | | | | | | | | Currently, when creating a named section, the Wasm frontend forces it to use `SectionKind::Data`, whereas in fact C++ does generate code sections with custom names. Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40906 llvm-svn: 320002
* [MC/Dwarf] Use the older DWARF linetables format on Darwin.Davide Italiano2017-12-073-12/+12
| | | | | | | | | | dsymutil doesn't yet understand the new format and the change, among others, breaks a large fraction of the debugger tests on mac OS. rdar://problem/35856354 llvm-svn: 319995
* [WebAssembly] Import the linear memory and function table.Dan Gohman2017-12-068-32/+39
| | | | | | | | | | | | Instead of having .o files contain linear-memory and function table definitions, use imports. This is more consistent with the stack pointer being imported, and it's consistent with the linker being the one to decide whether linear memory and function table are imported or defined in the linked output. This implements tool-conventions #23. Differential Revision: https://reviews.llvm.org/D40875 llvm-svn: 319989
* [mips] Fix definition of 'bc' instructionSimon Dardis2017-12-062-2/+4
| | | | llvm-svn: 319888
* [WebAssembly] Fix test breakage from r319810Derek Schuff2017-12-061-1/+1
| | | | llvm-svn: 319865
* [DWARFv5] Emit v5 line table header.Paul Robinson2017-12-051-3/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D40741 llvm-svn: 319827
* Re-submit r289925 (Update .debug_line section version to match DWARF version)Paul Robinson2017-12-048-25/+25
| | | | | | | | | | | | | | | Set the .debug_line version to match the requested DWARF version, except with a maximum of v4 because we don't support v5 yet. Previously Chromium had issues with this patch; see PR31407. Chromium tool issues have been addressed, so hopefully this will go through this time. Patch by Katya Romanova! Differential Revision: https://reviews.llvm.org/D38002 llvm-svn: 319699
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-0444-74/+74
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-0410-52/+49
| | | | | | | | This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
* [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-0410-49/+52
| | | | | | | | | | | | | | | | This adds a "invalid operands for instruction" diagnostic for instructions where there is an instruction encoding with the correct mnemonic and which is available for this target, but where multiple operands do not match those which were provided. This makes it clear that there is some combination of operands that is valid for the current target, which the default diagnostic of "invalid instruction" does not. Since this is a very general error, we only emit it if we don't have a more specific error. Differential revision: https://reviews.llvm.org/D36747 llvm-svn: 319649
* Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""Sam Clegg2017-12-031-0/+23
| | | | | | | | | | Original change was rL319488. This was reverted rL319602 due to a gcc 7.1 warning. Differential Revision: https://reviews.llvm.org/D40772 llvm-svn: 319626
* [X86] Fix copy paste mistake in test case for r319612.Craig Topper2017-12-021-1/+1
| | | | llvm-svn: 319613
* [X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.Craig Topper2017-12-021-0/+3
| | | | llvm-svn: 319612
* [X86] Support %dr8-%dr15 in the assembler.Craig Topper2017-12-021-0/+3
| | | | | | Apparently I failed to make this work when I fixed it in the disassembler way back in r224862. llvm-svn: 319611
* [ARC] Add instruction subset for the ARC backend.Tatyana Krasnukha2017-12-023-0/+394
| | | | | | | | | | | | Reviewers: petecoup, kparzysz Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37983 llvm-svn: 319609
* [WebAssembly] Revert r319488 "Add visibility flag to Wasm symbol flags"Heejin Ahn2017-12-021-23/+0
| | | | | | | | | This patch reportedly broke one of LLVM bots (ubuntu-gcc7.1-werror). See http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3369 for details. llvm-svn: 319602
* [MC] Handle unknown literal register numbers in .cfi_* directivesJake Ehrlich2017-12-011-0/+7
| | | | | | | | | | | | | | | | | r230670 introduced a step to map EH register numbers to standard DWARF register numbers. This failed to consider the case when a user .cfi_* directive uses an integer literal rather than a register name, to specify a DWARF register number that has no corresponding LLVM register number (e.g. a special register that the compiler and assembler have no name for). Fixes PR34028. Patch by Roland McGrath Differential Revision: https://reviews.llvm.org/D36493 llvm-svn: 319586
* [WebAssembly] Update MC tests now that hidden attr is supportedSam Clegg2017-12-013-7/+14
| | | | | | | | | | | | Summary: Support was added in rL319488 but these tests were not updated. Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D40693 llvm-svn: 319510
* Add visibility flag to Wasm symbol flagsSam Clegg2017-11-301-0/+23
| | | | | | | | | | | | | | The LLVM "hidden" flag needs to be passed through the Wasm intermediate objects in order for the linker to apply it to the final Wasm object. The corresponding change in LLD is here: https://github.com/WebAssembly/lld/pull/14 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40442 llvm-svn: 319488
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-292-29/+0
| | | | | | used by any instructions). llvm-svn: 319321
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-11-292-0/+29
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 319315
* [ARM] Add support for armv7e-m to the .arch directiveOliver Stannard2017-11-292-0/+66
| | | | | | | | | | | This will allow compilation of assembly files targeting armv7e-m without having to specify the Tag_CPU_arch attribute as a workaround. Differential revision: https://reviews.llvm.org/D40370 Patch by Ian Tessier! llvm-svn: 319303
* AMDGPU: Add num spilled s/vgprs to metadataKonstantin Zhuravlyov2017-11-281-0/+4
| | | | | | | | This was requested by tools. Differential Revision: https://reviews.llvm.org/D40321 llvm-svn: 319192
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-282-4/+4
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-271-0/+85
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-261-0/+169
| | | | | | | | | | | | | | | | | | Shadow stack solution introduces a new stack for return addresses only. The HW has a Shadow Stack Pointer (SSP) that points to the next return address. If we return to a different address, an exception is triggered. The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP). The intrinsics are mapped to new instruction set that implements CET mechanism. The patch also includes initial infrastructure support for IBT. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40223 Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4 llvm-svn: 318996
* [x86][icelake]GFNICoby Tayree2017-11-263-0/+786
| | | | | | | | | | galois field arithmetic (GF(2^8)) insns: gf2p8affineinvqb gf2p8affineqb gf2p8mulb Differential Revision: https://reviews.llvm.org/D40373 llvm-svn: 318993
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-242-0/+72
| | | | | | | | | | See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39488 llvm-svn: 318955
* [AVR] Use the short form of 'clr <reg>'Dylan McKay2017-11-241-4/+5
| | | | | | | r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-241-0/+10
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility ↵Dmitry Preobrazhensky2017-11-241-0/+4
| | | | | | | | | | | | with SP3 See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329 Reviewers: arsenm, vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D40350 llvm-svn: 318947
* [x86][icelake]BITALGCoby Tayree2017-11-232-0/+168
| | | | | | | | | | 2/3 vpshufbitqmb encoding 3/3 vpshufbitqmb intrinsics Differential Revision: https://reviews.llvm.org/D40222 llvm-svn: 318904
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-224-6/+6
| | | | llvm-svn: 318875
* [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9Dmitry Preobrazhensky2017-11-224-0/+9714
| | | | | | | | Summary: Added tests to better cover features introduced by commit rL318675. See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675 llvm-svn: 318841
* [DWARF] Fix handling of extended line-number opcodesPaul Robinson2017-11-221-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D40200 llvm-svn: 318838
* Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-214-16/+16
| | | | | | | | | | | | | | | | | Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Recommiting with missing clang inline assembly test change. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318797
* [ARM] Remove pre-UAL FLDM/FSTM aliasesOliver Stannard2017-11-213-112/+8
| | | | | | | | | | | | | These are pre-UAL syntax, and we don't support any other pre-UAL instructions, with the exception of FLDMX/FSTMX, which don't have a UAL equivalent. Therefore there's no reason to keep them or their AsmParser hacks around. With the AsmParser hacks removed, the FLDMX and FSTMX instructions get the same operand diagnostics as the UAL instructions. Differential revision: https://reviews.llvm.org/D39196 llvm-svn: 318777
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