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* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-172-20/+349
| | | | | | | | | See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771 Differential Revision: https://reviews.llvm.org/D42058 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322655
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-171-1/+37
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC ↵Gadi Haber2018-01-1614-0/+16124
| | | | | | | | | | | | | | | encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC> NFC. Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. Started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D40879 Change-Id: I231a35861611bfd3d23c74cc59507373f021a629 llvm-svn: 322544
* [DebugInfo] Unify dumping of address rangesJonas Devlieghere2018-01-164-6/+6
| | | | | | | | | | | | | | | Summary: This patch unifies the printing of address ranges as [0x0, 0x1). rdar://34822059 Reviewers: aprantl, dblaikie Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D42056 llvm-svn: 322543
* [X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>Gadi Haber2018-01-1611-0/+614
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover the XSAVE ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D41282 Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45 llvm-svn: 322537
* [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.Craig Topper2018-01-161-2/+2
| | | | | | Previously we encoded it as 0x48 0x90. llvm-svn: 322531
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-152-34/+63
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 ↵Gadi Haber2018-01-152-0/+70464
| | | | | | | | | | | | | | | bits isa sets.<NFC> NFC. Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41172 Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39 llvm-svn: 322471
* AMDGPU/SI: Add d16 support for buffer intrinsics.Changpeng Fang2018-01-122-0/+147
| | | | | | | | | | Differential Revision: https://reviews.llvm.org/D38906 Reviewers: Matt and Brian. llvm-svn: 322402
* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-122-41/+41
| | | | | | While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-121-0/+117
| | | | | | | | | | | | | | | | Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
* Tighten up DIFile verifier for checksumsPaul Robinson2018-01-111-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D41965 llvm-svn: 322314
* [WebAssemlby] MC: Don't write COMDAT symbols as global importsSam Clegg2018-01-111-2/+36
| | | | | | | | This was causing undefined references at link time in lld. Differential Revision: https://reviews.llvm.org/D41959 llvm-svn: 322309
* [WebAssemly] Rename and improve formatting for ctor/dtor testSam Clegg2018-01-111-3/+8
| | | | llvm-svn: 322307
* Implementation of X86Operand::print.Andrew V. Tischenko2018-01-111-40/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D41610 llvm-svn: 322267
* [Mips] Handle one byte unsupported relocationsStefan Maksimovic2018-01-111-0/+13
| | | | | | | | | Fail gracefully instead of crashing upon encountering this type of relocation. Differential revision: https://reviews.llvm.org/D41857 llvm-svn: 322266
* [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraintsSander de Smalen2018-01-112-1/+47
| | | | | | | | | | | | | | Summary: Patch [3/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: rengolin, fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41447 llvm-svn: 322265
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-103-1/+46
| | | | | | | | | See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322189
* [AArch64][SVE] Asm: Add support for (mov|dup) of scalarSander de Smalen2018-01-104-0/+150
| | | | | | | | | | | | | | Summary: This patch adds support for 'dup' (Scalar -> SVE) and its corresponding 'mov' alias. Reviewers: fhahn, rengolin, evandro, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41822 llvm-svn: 322172
* Reland "Emit Function IDs table for Control Flow Guard"Adrian McCarthy2018-01-091-0/+15
| | | | | | | | | | | | | | | | | Adds option /guard:cf to clang-cl and -cfguard to cc1 to emit function IDs of functions that have their address taken into a section named .gfids$y for compatibility with Microsoft's Control Flow Guard feature. The original patch didn't have the lit.local.cfg file that restricts the new test to x86, thus the new test was failing on the non-x86 bots. Differential Revision: https://reviews.llvm.org/D40531 The reverts r322008, which was a revert of r322005. This reverts commit a05b89f9aca70597dc79fe97bc49b50b51f525ba. llvm-svn: 322136
* [WebAssembly] Add COMDAT supportSam Clegg2018-01-091-0/+99
| | | | | | | | | | | | | | This adds COMDAT support to the Wasm object-file format. Spec: https://github.com/WebAssembly/tool-conventions/pull/31 Corresponding LLD change: https://bugs.llvm.org/show_bug.cgi?id=35533, and D40845 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40844 llvm-svn: 322135
* [DWARFv5] MC support for MD5 file checksumsPaul Robinson2018-01-092-0/+39
| | | | | | | Extend .file directive syntax to allow specifying an MD5 checksum for the source file. Emit the checksums in DWARF v5 line tables. llvm-svn: 322134
* Use a MCExpr for the size of MCFillFragment.Rafael Espindola2018-01-091-0/+17
| | | | | | | This allows the size to be found during ralaxation. This fixes pr35858. llvm-svn: 322131
* [WebAssembly] MC: Use zero for provisional value of undefined symbolsSam Clegg2018-01-092-3/+3
| | | | | | | | | | This is more in line with what happens in the final executable when symbols are undefined (i.e. weak references). Differential Revision: https://reviews.llvm.org/D41840 llvm-svn: 322130
* Add a test.Rafael Espindola2018-01-091-0/+4
| | | | | | Currently we don't have any tests for this error case. llvm-svn: 322129
* [WebAssembly] Explicitly specify function/global index space in YAMLSam Clegg2018-01-095-25/+50
| | | | | | | | | | | These indexes are useful because they are not always zero based and functions and globals are referenced elsewhere by their index. This matches what we already do for the type index space. Differential Revision: https://reviews.llvm.org/D41877 llvm-svn: 322121
* Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-094-0/+262
| | | | | | | | | Fixed issue that was found on sanitizer-x86_64-linux-fast. I changed the result type of 'Parser.getTok().getString().lower()' in AArch64AsmParser::tryParseSVEPredicateVector() from 'StringRef' to 'auto', since StringRef::lower() returns a std::string. llvm-svn: 322092
* Reverted r322073 because of AddressSanitizer failure onSander de Smalen2018-01-094-262/+0
| | | | | | sanitizer-x86_64-linux-fast builder. llvm-svn: 322077
* [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-094-0/+262
| | | | | | | | | | | | | | | | | Summary: Add the predicated ADD/SUB instructions and corresponding tests. Patch [3/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41443 llvm-svn: 322073
* Instrument Control Flow For Indirect Branch TrackingOren Ben Simhon2018-01-091-1/+9
| | | | | | | | | | | | | CET (Control-Flow Enforcement Technology) introduces a new mechanism called IBT (Indirect Branch Tracking). According to IBT, each Indirect branch should land on dedicated ENDBR instruction (End Branch). The new pass adds ENDBR instructions for every indirect jmp/call (including jumps using jump tables / switches). For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40482 Change-Id: Icb754489faf483a95248f96982a4e8b1009eb709 llvm-svn: 322062
* Revert "Emit Function IDs table for Control Flow Guard"Adrian McCarthy2018-01-081-15/+0
| | | | | | | | | | The new test fails on the Hexagon bot. Reverting while I investigate. This reverts https://reviews.llvm.org/rL322005 This reverts commit b7e0026b4385180c378edc658ec91a39566f2942. llvm-svn: 322008
* Emit Function IDs table for Control Flow GuardAdrian McCarthy2018-01-081-0/+15
| | | | | | | | | | Adds option /guard:cf to clang-cl and -cfguard to cc1 to emit function IDs of functions that have their address taken into a section named .gfids$y for compatibility with Microsoft's Control Flow Guard feature. Differential Revision: https://reviews.llvm.org/D40531 llvm-svn: 322005
* [X86] Remove memory forms of EVEX encoded vcvttss2si/vcvttsd2si from asm ↵Craig Topper2018-01-061-8/+8
| | | | | | | | matcher table. This is also needed to fix PR35837. llvm-svn: 321946
* [X86] Remove memory forms of EVEX encoded vcvtsd2si/vcvtss2si from the ↵Craig Topper2018-01-061-4/+4
| | | | | | | | | | assembler matcher table We should always prefer the VEX encoded version of these instructions. There is no advantage to the EVEX version. Fixes PR35837. llvm-svn: 321939
* [X86] When parsing rounding mode operands, provide a proper end location so ↵Craig Topper2018-01-061-0/+3
| | | | | | we don't crash when trying to print an error message using it. llvm-svn: 321930
* [X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded ↵Craig Topper2018-01-051-0/+64
| | | | | | | | instructions. This matches their VEX equivalents. llvm-svn: 321912
* [X86] Add InstAliases for 'vmovd' with GR64 registers to select EVEX encoded ↵Craig Topper2018-01-051-0/+8
| | | | | | | | | | instructions as well. Without this we allow "vmovd %rax, %xmm0", but not "vmovd %rax, %xmm16" This exists due to continue a silly bug where really old versions of the GNU assembler required movd instead of movq on these instructions. This compatibility hack then crept forward to avx version too, but we didn't propagate it to avx512. llvm-svn: 321903
* [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use ↵Craig Topper2018-01-053-12/+36
| | | | | | | | 'movq' instead. This behavior existed to work with an old version of the gnu assembler on MacOS that only accepted this form. Newer versions of GNU assembler and the current LLVM derived version of the assembler on MacOS support movq as well. llvm-svn: 321898
* [ARM] Issue an erorr when non-general-purpose registers are used in address ↵Momchil Velikov2018-01-051-0/+50
| | | | | | | | | | | | operands Currently the assembler would accept, e.g. `ldr r0, [s0, #12]` and similar. This patch add checks that only general-purpose registers are used in address operands, shifted registers, and shift amounts. Differential revision: https://reviews.llvm.org/D39910 llvm-svn: 321866
* [ARM] Fix endianness of Thumb .inst.w directiveOliver Stannard2018-01-041-6/+13
| | | | | | | | | Wide Thumb2 instructions should be emitted into the object file as pairs of 16-bit words of the appropriate endianness, not one 32-bit word. Differential revision: https://reviews.llvm.org/D41185 llvm-svn: 321799
* [MC] - Stop ignoring invalid meta data symbols.George Rimar2017-12-311-0/+10
| | | | | | | | | | | Previously llvm-mc would silently accept code from testcase, that contains invalid metadata symbol in section declaration. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D41641 llvm-svn: 321599
* [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiersDmitry Preobrazhensky2017-12-292-0/+60
| | | | | | | | | See bug 35730: https://bugs.llvm.org/show_bug.cgi?id=35730 Differential Revision: https://reviews.llvm.org/D41598 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 321552
* Fix incorrect operand sizes for some MMX instructions: punpcklwd, punpcklbw ↵Andrew V. Tischenko2017-12-293-2/+20
| | | | | | | | and punpckldq. Differential Revision: https://reviews.llvm.org/D41595 llvm-svn: 321549
* Fix tests after move to utohexstr.Benjamin Kramer2017-12-281-2/+2
| | | | llvm-svn: 321527
* [X86][PREFETCH]: Adding full coverage of MC encoding for the PREFETCH isa ↵Gadi Haber2017-12-282-0/+339
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the PREFETCH isa sets for both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41161 Change-Id: Icdc8c5fb68c414de7d2cfdb50da1cc6763d9932a llvm-svn: 321524
* A special test to demonstrate debug logging for asm matcher.Andrew V. Tischenko2017-12-271-0/+52
| | | | llvm-svn: 321497
* [X86][RD]: Adding full coverage of MC encoding for RD isa sets.<NFC>Gadi Haber2017-12-279-0/+98
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover RDPMC, RDRAND, RDRAND, RDSEED, RDTSCP, DWRFSGS isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenk Differential Revision: https://reviews.llvm.org/D41328 Change-Id: Ie97b397546e6b1ed180c6abd7b41fccb136d2b82 llvm-svn: 321476
* It's a fix for Bug 35741 - can't use comments after x86 prefixes.Andrew V. Tischenko2017-12-261-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D41579 llvm-svn: 321459
* [MC] - Disallow invalid section groups declarations.George Rimar2017-12-251-0/+14
| | | | | | | | | | | | This fixes parseGroup() so that it always sets error condition on error. Previously it was not done, because parseIdentifier looks never do that, assuming that caller should do it if he wants to. So previously cases from test were silently accepted and produced broken output. Differential revision: https://reviews.llvm.org/D41559 llvm-svn: 321439
* [MC] - Teach llvm-mc to handle comdats whose names are numbers.George Rimar2017-12-241-0/+28
| | | | | | | | | | | | | | | Currently llvm-mc ignores COMDATs whose names are numbers, for example following code: .section .foo,"G",@progbits,123,comdat would produce no COMDATs at all. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D41552 llvm-svn: 321419
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