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* [mips] Correct the definition of m(f|t)c(0|2)Simon Dardis2018-03-0710-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-065-12/+48
| | | | | | | | Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. llvm-svn: 326839
* [AMDGPU] Add default ISA version targetsStanislav Mekhanoshin2018-03-061-0/+6
| | | | | | | | | | | In case if -mattr used to modify feature set bits in llvm-mc call getIsaVersion can fail to identify specific ISA due to test mismatch. Adding default fallback tests which will always correctly report at least major version. Differential Revision: https://reviews.llvm.org/D44163 llvm-svn: 326825
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-062-4/+10
| | | | | | | | | | | | | | | This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 llvm-svn: 326803
* Revert "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-065-48/+14
| | | | | | | | | Caused an asan failure. This reverts commit d54883f081186cdcce74e6f98cfc0438579ec019. aka r326758 llvm-svn: 326762
* [DWARFv5] Emit file 0 to the line table.Paul Robinson2018-03-065-14/+48
| | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 326758
* [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registersOliver Stannard2018-03-051-0/+6
| | | | | | | | | | These instructions require that the two S registers are adjacent (but not the R registers), because only the first register is included in the encoding, but we were not checking this in the assembler. Differential revision: https://reviews.llvm.org/D44084 llvm-svn: 326696
* [RISCV] Implement MC relaxations for compressed instructions.Sameer AbuAsal2018-03-024-3/+151
| | | | | | | | | | | | | | | | | | Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
* [WebAssembly] Avoid cast ExprType to wasm::ValTypeSam Clegg2018-03-021-0/+30
| | | | | | | | | | | This cast was causing invalid signatures to be written for libcall functions. Add an MC test which includes a call to builtin memcpy. Differential Revision: https://reviews.llvm.org/D44037 llvm-svn: 326618
* Revert "[WebAssembly] More uses of uint8_t" and "[WebAssembly] Update tests"Nicholas Wilson2018-03-021-9/+9
| | | | | | | | | | This reverts commits r326541 and r326571. The tests were correct, and were updated with incorrect expectations. The original commit was broken and should be reverted to get things back to a working state. llvm-svn: 326572
* [WebAssembly] Update tests after r326541Ilya Biryukov2018-03-021-9/+9
| | | | | | | | | | r326541 slightly increased the size of WebAssembly object files and it broke test/MC/WebAssembly/global-ctor-dtor.ll. This commit updates the test to unbreak it, also mentioned this to the author of the original commit in case they don't want it. llvm-svn: 326571
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-012-1/+13
| | | | llvm-svn: 326492
* [AArch64] Add support for secrel add/load/store relocations for COFFMartin Storsjo2018-03-011-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D43288 llvm-svn: 326480
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-011-0/+67
| | | | llvm-svn: 326450
* [WebAssembly] Reorder symbol table to match MC orderNicholas Wilson2018-02-289-80/+80
| | | | | | | | This removes a TODO introduced in rL325860 Differential Revision: https://reviews.llvm.org/D43685 llvm-svn: 326334
* [WebAssembly] Remove DataSize from linking metadata sectionSam Clegg2018-02-279-9/+0
| | | | | | | | | | | Neither the linker nor the runtime need this information anymore. We were originally using this to model BSS size but the plan is now to use the segment metadata to allow for BSS segments. Differential Revision: https://reviews.llvm.org/D41366 llvm-svn: 326267
* [DebugInfo] Remove target-specific instructions in testScott Linder2018-02-261-2/+0
| | | | | | | This AsmParser test is target-agnostic, but contained some target-specific instructions, which broke on SystemZ. llvm-svn: 326129
* bpf: New disassembler testcases for 32-bit subregister supportYonghong Song2018-02-233-7/+40
| | | | | | | | | | | | This patch test disassembler output for load/store instructions when -mattr=+alu32 specified for which we want to use "w" register format. Also, this patch extended the existing insn-unit.s and insn-unit-32.s to make sure disassemblers for all other instructions are not affected. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325993
* [DebugInfo] Add remaining files to r325970Scott Linder2018-02-234-0/+80
| | | | | | Add files which I missed in the original check-in llvm-svn: 325973
* [DebugInfo] Support DWARF v5 source code embedding extensionScott Linder2018-02-235-16/+28
| | | | | | | | | | | | | | | | | | | In DWARF v5 the Line Number Program Header is extensible, allowing values with new content types. In this extension a content type is added, DW_LNCT_LLVM_source, which contains the embedded source code of the file. Add new optional attribute for !DIFile IR metadata called source which contains source text. Use this to output the source to the DWARF line table of code objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM to support optional source. Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output format of llvm-dwarfdump to make room for the new attribute on file_names entries, and support embedded sources for the -source option in llvm-objdump. Differential Revision: https://reviews.llvm.org/D42765 llvm-svn: 325970
* [X86] Add assembler/disassembler support for blendm with zero masking and ↵Craig Topper2018-02-232-0/+184
| | | | | | | | broacast. Fixes PR31617 llvm-svn: 325957
* [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.Stefan Pintilie2018-02-232-33/+1
| | | | | | | | | | | | | | The following set of instructions was originally planned to be added for Power 9 and so code was added to support them. However, a decision was made later on to withdraw support for these instructions in the hardware. xscmpnedp xvcmpnesp xvcmpnedp This patch removes support for the instructions that were not added. Differential Revision: https://reviews.llvm.org/D43641 llvm-svn: 325918
* [WebAssembly] Add first claass symbol table to wasm objectsSam Clegg2018-02-2313-333/+282
| | | | | | | | | | | | | | | | | | | | This is combination of two patches by Nicholas Wilson: 1. https://reviews.llvm.org/D41954 2. https://reviews.llvm.org/D42495 Along with a few local modifications: - One change I made was to add the UNDEFINED bit to the binary format to avoid the extra byte used when writing data symbols. Although this bit is redundant for other symbols types (i.e. undefined can be implied if a function or global is a wasm import) - I prefer to be explicit and consistent and not have derived flags. - Some field renaming. - Some reverting of unrelated minor changes. - No test output differences. Differential Revision: https://reviews.llvm.org/D43147 llvm-svn: 325860
* [DWARFv5] Turn an assert into a diagnostic. Hand-coded assembler filesPaul Robinson2018-02-221-0/+5
| | | | | | | | should not trigger assertions. Differential Revision: https://reviews.llvm.org/D43152 llvm-svn: 325831
* [MC] Don't crash on modulo by zero (PR35650)Simon Pilgrim2018-02-221-0/+3
| | | | | | | | Extension to D12776, handle modulo by zero in the same way we handle divide by zero. Differential Revision: https://reviews.llvm.org/D43631 llvm-svn: 325810
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-222-5/+13
| | | | | | | | | | | | Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff]. Differential Revision: https://reviews.llvm.org/D42834 llvm-svn: 325792
* [AMDGPU][MC] Added lds support for MUBUF instructionsDmitry Preobrazhensky2018-02-212-3/+112
| | | | | | | | | See bug 28234: https://bugs.llvm.org/show_bug.cgi?id=28234 Differential Revision: https://reviews.llvm.org/D43472 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 325676
* [mips] Correct the definition of cvt.d.wSimon Dardis2018-02-202-4/+8
| | | | | | | | An upcoming patch D41434, changes the ordering of the matcher table for assembly. This patch corrects the definition of the normal MIPS cvt.d.w not to be available in microMIPS. llvm-svn: 325589
* [llvm-mc] - Produce R_X86_64_PLT32 for "call/jmp foo".George Rimar2018-02-205-12/+14
| | | | | | | | | | | For instructions like call foo and jmp foo patch changes relocation produced from R_X86_64_PC32 to R_X86_64_PLT32. Relocation can be used as a marker for 32-bit PC-relative branches. Linker will reduce PLT32 relocation to PC32 if function is defined locally. Differential revision: https://reviews.llvm.org/D43383 llvm-svn: 325569
* [MC] - Don't crash on unclosed frame.George Rimar2018-02-201-0/+10
| | | | | | | | | | | | | | | | llvm-mc can crash when there is cfi_startproc without cfi_end_proc: .text .globl foo foo: .cfi_startproc Testcase shows the issue, patch fixes it. Differential revision: https://reviews.llvm.org/D43456 llvm-svn: 325564
* [X86][CET]: Adding full coverage of MC encoding for the CET instructions.<NFC>Gadi Haber2018-02-202-0/+300
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover the CET instructions. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko, oren_ben_simhon Differential Revision: https://reviews.llvm.org/D41329 Change-Id: I9c133d4ba07508ce8fd738a1230edd586e2c2f1b llvm-svn: 325561
* [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168)Simon Pilgrim2018-02-171-0/+3
| | | | llvm-svn: 325435
* AMDGPU: Bring processors and features in sync with the specKonstantin Zhuravlyov2018-02-164-28/+28
| | | | | | | | | | - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
* [WebAssembly] MC: Make explicit our current lack of support for relocations ↵Sam Clegg2018-02-161-0/+15
| | | | | | | | | | | | against unnamed temporary symbols. Add an explicit check before looking up symbol in SymbolIndices. This was previously silently succeeding and returning zero for such unnamed temporaries. Differential Revision: https://reviews.llvm.org/D43365 llvm-svn: 325367
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-151-0/+76
| | | | | | | | | | | | | | | | | | | Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
* [X86] Change 32 and 64 bit versions of LSL instruction have a 16-bit memory ↵Craig Topper2018-02-151-0/+8
| | | | | | | | operand. This matches the Intel and AMD documentation and is consistent with the LAR instruction. llvm-svn: 325197
* [X86] Dont' allow 'outs' and 'ins' in at&t syntax without suffixes.Craig Topper2018-02-142-9/+0
| | | | | | The match would be ambiguous, but at&t asm parsing doesn't support ambiguous matches and will just return the first. llvm-svn: 325192
* [X86] Don't use 64 bit hex constants in a 32 bit assembler test.Craig Topper2018-02-141-51/+0
| | | | llvm-svn: 325191
* [X86] Reverse the operand order of invlpga in at&t syntax to match gas.Craig Topper2018-02-144-8/+8
| | | | llvm-svn: 325190
* [X86] Don't swap argument on BOUND instruction in at&t syntax.Craig Topper2018-02-144-22/+22
| | | | | | | | | | | | The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
* Store defined macros in MCContext.Rafael Espindola2018-02-141-0/+8
| | | | | | | | | | | | | | | So that macros defined in inline assembly blocks are available to the whole file. This provides a consistent behavior with other assembly directives, since equations for example are already preserved between inline assembly blocks. PR: 36110 Patch by Roger! llvm-svn: 325139
* [ARM] Don't print "Requires NEON" error message for M-profileAndre Vieira2018-02-131-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D43125 llvm-svn: 325000
* [MC] Issue error message when data region is not terminatedGerolf Hoflehner2018-02-121-0/+8
| | | | llvm-svn: 324868
* REQUIRES: shell a couple of tests that require the shellDavid Blaikie2018-02-101-0/+1
| | | | | | | | One test uses diff, the other tries to change the PATH which doesn't seem to work well ('not' is no longer accessible/found after the PATH is changed - I think $PATH isn't expanded when setting PATH). llvm-svn: 324787
* [WebAssembly] Add mechanisms for specifying an explicit import module name.Dan Gohman2018-02-091-1/+8
| | | | | | | | | | | | | | | | | | | | This adds a wasm-import-module function attribute and a .import_module assembler directive, for specifying module import names for WebAssembly. Currently these may only be used for function symbols; global variables may be considered in the future. WebAssembly has a two-level namespace scheme for symbols, and it's normally the linker's job to assign the module name, which is the first-level name. The attributes here allow users to specify their own module names explicitly, which is useful for tools generating bindings to modules defined in other languages. This feature is not fully usable yet. It will evolve along with the ongoing symbol table and lld changes. Differential Revision: https://reviews.llvm.org/D42520 llvm-svn: 324778
* [X86][MC] Fix assembling rip-relative addressing + immediate displacementsFrancis Visoiu Mistrih2018-02-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the rare case where the input contains rip-relative addressing with immediate displacements, *and* the instruction ends with an immediate, we encode the instruction in the wrong way: movl $12345678, 0x400(%rdi) // all good, no rip-relative addr movl %eax, 0x400(%rip) // all good, no immediate at the end of the instruction movl $12345678, 0x400(%rip) // fails, encodes address as 0x3fc(%rip) Offset is a label: movl $12345678, foo(%rip) we want to account for the size of the immediate (in this case, $12345678, 4 bytes). Offset is an immediate: movl $12345678, 0x400(%rip) we should not account for the size of the immediate, assuming the immediate offset is what the user wanted. Differential Revision: https://reviews.llvm.org/D43050 llvm-svn: 324772
* [WebAssebmly] Report undefined symbols correctly in objdumpSam Clegg2018-02-091-10/+10
| | | | | | | | | | | | | | Peviously we were reporting undefined symbol as being defined by the IMPORT sections. This change reports undefined symbols in the same that other formats do, and also removes the need to store the section with each symbol (since it can be derived from the symbol type). Differential Revision: https://reviews.llvm.org/D43101 llvm-svn: 324770
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-4/+4
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [ELF] Print the .type assembly directive correctly for STT_NOTYPEOliver Stannard2018-02-091-0/+17
| | | | | | | | | | The llvm assembly parser and gas both accept "@notype" in the .type assembly directive, but we were printing it as "@no_type", which isn't accepted by either assembler. Differential revision: https://reviews.llvm.org/D43116 llvm-svn: 324731
* Make test changes added in r324584 more robust by using a regex instead of ↵Douglas Yung2018-02-096-66/+66
| | | | | | hard coded MCInst numbers. llvm-svn: 324699
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