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* [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_doneDmitry Preobrazhensky2018-04-062-3/+15
| | | | | | | | | See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844 Differential Revision: https://reviews.llvm.org/D45313 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329430
* [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*Dmitry Preobrazhensky2018-04-062-64/+141
| | | | | | | | | See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840 Differential Revision: https://reviews.llvm.org/D45250 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329419
* [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructionsDmitry Preobrazhensky2018-04-062-0/+28
| | | | | | | | | See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839 Differential Revision: https://reviews.llvm.org/D45249 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329408
* [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.Pete Couperus2018-04-061-0/+24
| | | | | | | | | Add disassembler support for instructions which writeback STATUS32. https://reviews.llvm.org/D45148 Patch by Yan Luo! (Yan.Luo2@synopsys.com) llvm-svn: 329404
* [AMDGPU][MC][GFX9] Added s_dcache_discard* instructionsDmitry Preobrazhensky2018-04-062-0/+36
| | | | | | | | | See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838 Differential Revision: https://reviews.llvm.org/D45247 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329397
* [WebAssembly] Allow for the creation of user-defined custom sectionsSam Clegg2018-04-051-0/+23
| | | | | | | | | | | | | This patch adds a way for users to create their own custom sections to be added to wasm files. At the LLVM IR layer, they are defined through the "wasm.custom_sections" named metadata. The expected use case for this is bindings generators such as wasm-bindgen. Patch by Dan Gohman Differential Revision: https://reviews.llvm.org/D45297 llvm-svn: 329315
* [WebAssembly] Only write 32-bits for WebAssembly::OPERAND_OFFSET32Sam Clegg2018-04-041-0/+21
| | | | | | | | | A bug was found where an offset of -1 would generate an encoding of max int64 which is invalid in the binary format. Differential Revision: https://reviews.llvm.org/D45280 llvm-svn: 329238
* [AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CIDmitry Preobrazhensky2018-04-041-0/+4
| | | | | | | | | See bug 36958: https://bugs.llvm.org/show_bug.cgi?id=36958 Differential Revision: https://reviews.llvm.org/D45099 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329197
* [AMDGPU][MC] Added support of 3-element addresses for MIMG instructionsDmitry Preobrazhensky2018-04-041-0/+63
| | | | | | | | | See bug 35999: https://bugs.llvm.org/show_bug.cgi?id=35999 Differential Revision: https://reviews.llvm.org/D45084 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329187
* [ARM] Do not convert some vmov instructionsMikhail Maltsev2018-04-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Patch https://reviews.llvm.org/D44467 implements conversion of invalid vmov instructions into valid ones. It turned out that some valid instructions also get converted, for example vmov.i64 d2, #0xff00ff00ff00ff00 -> vmov.i16 d2, #0xff00 Such behavior is incorrect because according to the ARM ARM section F2.7.7 Modified immediate constants in T32 and A32 Advanced SIMD instructions, "On assembly, the data type must be matched in the table if possible." This patch fixes the isNEONmovReplicate check so that the above instruction is not modified any more. Reviewers: rengolin, olista01 Reviewed By: rengolin Subscribers: javed.absar, kristof.beyls, rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D44678 llvm-svn: 329158
* Remove llvm-mcmarkup.Eric Christopher2018-04-022-18/+0
| | | | | | It was never used and I've checked with the original authors. llvm-svn: 329029
* [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16Dmitry Preobrazhensky2018-04-027-0/+152
| | | | | | | | | See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847 Differential Revision: https://reviews.llvm.org/D45097 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328988
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-022-0/+456
| | | | | | | | | | | Fixed a bug which caused Tablegen crash. See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837 Differential Revision: https://reviews.llvm.org/D45085 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328983
* Revert r328975, it makes TableGen assert on the bots.Nico Weber2018-04-022-456/+0
| | | | llvm-svn: 328978
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-022-0/+456
| | | | | | | | | See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837 Differential Revision: https://reviews.llvm.org/D45085 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328975
* [Hexagon] Recognize and handle :endloop01Krzysztof Parzyszek2018-03-301-3/+10
| | | | llvm-svn: 328870
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-295-12/+48
| | | | | | | | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. We emit the new syntax only for DWARF v5 and later. Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. Last but not least, don't break "clang -g" of an assembler file that has .file directives in it. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 328805
* [AMDGPU][MC] Added ds_add_src2_f32Dmitry Preobrazhensky2018-03-282-0/+11
| | | | | | | | | See bug 36833: https://bugs.llvm.org/show_bug.cgi?id=36833 Differential Revision: https://reviews.llvm.org/D44779 Reviewers: arsenm, artem.tamazov, timcorringham llvm-svn: 328713
* [AMDGPU][MC] Added PCK variants of image load/store instructionsDmitry Preobrazhensky2018-03-282-0/+69
| | | | | | | | | See bug 36834: https://bugs.llvm.org/show_bug.cgi?id=36834 Differential Revision: https://reviews.llvm.org/D44795 Reviewers: artem.tamazov, arsenm, timcorringham, nhaehnle llvm-svn: 328710
* [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_xDmitry Preobrazhensky2018-03-282-0/+70
| | | | | | | | | See bug 36835: https://bugs.llvm.org/show_bug.cgi?id=36835 Differential Revision: https://reviews.llvm.org/D44825 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328707
* [AMDGPU][MC][GFX9] Added s_scratch* instructionsDmitry Preobrazhensky2018-03-282-24/+116
| | | | | | | | | See bug 36836: https://bugs.llvm.org/show_bug.cgi?id=36836 Differential Revision: https://reviews.llvm.org/D44832 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328704
* Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""Alexander Potapenko2018-03-285-48/+12
| | | | | | | | | | | | | | | This reverts commit r328676. Commit r328676 broke the -no-integrated-as flag necessary to build Linux kernel with Clang: $ cat t.c void foo() {} $ clang -no-integrated-as -c t.c -g /tmp/t-dcdec5.s: Assembler messages: /tmp/t-dcdec5.s:8: Error: file number less than one clang-7.0: error: assembler command failed with exit code 1 (use -v to see invocation) llvm-svn: 328699
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-275-12/+48
| | | | | | | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. Last but not least, don't break "clang -g" of an assembler file that has .file directives in it. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 328676
* Use .set instead of = when printing assignment in assembly outputKrzysztof Parzyszek2018-03-277-12/+23
| | | | | | | | | On Hexagon "x = y" is a syntax used in most instructions, and is not treated as a directive. Differential Revision: https://reviews.llvm.org/D44256 llvm-svn: 328635
* [AMDGPU] Improve disassembler error handlingTim Corringham2018-03-261-0/+27
| | | | | | | | | | | | | | | | | | | | | | Summary: llvm-objdump now disassembles unrecognised opcodes as data, using the .long directive. We treat unrecognised opcodes as being 32 bit values, so move along 4 bytes rather than the single byte which previously resulted in a cascade of bogus disassembly following an unrecognised opcode. While no solution can always disassemble code that contains embedded data correctly this provides a significant improvement. The disassembler will now cope with an arbitrary length section as it no longer truncates it to a multiple of 4 bytes, and will use the .byte directive for trailing bytes. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D44685 llvm-svn: 328553
* Add REQUIRES lines for the targets being checked in this test.Eric Christopher2018-03-241-0/+3
| | | | llvm-svn: 328408
* Allow FDE references outside the +/-2GB range supported by PC relativeEric Christopher2018-03-241-21/+44
| | | | | | | | | | offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise. Patch based on one by Olexa Bilaniuk! llvm-svn: 328400
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-231-4/+3
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [ARM] Error out on .arm assembler directives on windowsMartin Storsjo2018-03-231-0/+3
| | | | | | | | Windows on arm is thumb only. Differential Revision: https://reviews.llvm.org/D43005 llvm-svn: 328298
* [DWARF] Fix mixing assembler -g with DWARF .file directives.Paul Robinson2018-03-221-1/+1
| | | | | | | | | | | We were effectively overriding an explicit '.file' directive with info for the assembler source. That shouldn't happen. Fixes PR36636, really, even for .s files emitted by Clang. Differential Revision: https://reviews.llvm.org/D44265 llvm-svn: 328208
* [WebAssembly] Added initial AsmParser implementation.Derek Schuff2018-03-201-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It uses the MC framework and the tablegen matcher to do the heavy lifting. Can handle both explicit and implicit locals (-disable-wasm-explicit-locals). Comes with a small regression test. This is a first basic implementation that can parse most llvm .s output and round-trips most instructions succesfully, but in order to keep the commit small, does not address all issues. There are a fair number of mismatches between what MC / assembly matcher think a "CPU" should look like and what WASM provides, some already have workarounds in this commit (e.g. the way it deals with register operands) and some that require further work. Some of that further work may involve changing what the Disassembler outputs (and what s2wasm parses), so are probably best left to followups. Some known things missing: - Many directives are ignored and not emitted. - Vararg calls are parsed but extra args not emitted. - Loop signatures are likely incorrect. - $drop= is not emitted. - Disassembler does not output SIMD types correctly, so assembler can't test them. Patch by Wouter van Oortmerssen Differential Revision: https://reviews.llvm.org/D44329 llvm-svn: 328028
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-171-0/+12
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* [IR] Avoid the need to prefix MS C++ symbols with '\01'Reid Kleckner2018-03-161-17/+0
| | | | | | | | | | | | | | | | | | | | Now the Windows mangling modes ('w' and 'x') do not do any mangling for symbols starting with '?'. This means that clang can stop adding the hideous '\01' leading escape. This means LLVM debug logs are less likely to contain ASCII escape characters and it will be easier to copy and paste MS symbol names from IR. Finally. For non-Windows platforms, names starting with '?' still get IR mangling, so once clang stops escaping MS C++ names, we will get extra '_' prefixing on MachO. That's fine, since it is currently impossible to construct a triple that uses the MS C++ ABI in clang and emits macho object files. Differential Revision: https://reviews.llvm.org/D7775 llvm-svn: 327734
* [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP ↵Dmitry Preobrazhensky2018-03-162-41/+41
| | | | | | | | | | | opcodes See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751 Differential Revision: https://reviews.llvm.org/D44529 Reviewers: artem.tamazov, arsenm llvm-svn: 327723
* [AMDGPU][MC] Corrected default values for unused SDWA operandsDmitry Preobrazhensky2018-03-168-30668/+62378
| | | | | | | | | See bug 36355: https://bugs.llvm.org/show_bug.cgi?id=36355 Differential Revision: https://reviews.llvm.org/D44481 Reviewers: artem.tamazov, arsenm llvm-svn: 327720
* [ARM] Convert more invalid NEON immediate loadsMikhail Maltsev2018-03-162-31/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently the LLVM MC assembler is able to convert e.g. vmov.i32 d0, #0xabababab (which is technically invalid) into a valid instruction vmov.i8 d0, #0xab this patch adds support for vmov.i64 and for cases with the resulting load types other than i8, e.g.: vmov.i32 d0, #0xab00ab00 -> vmov.i16 d0, #0xab00 Reviewers: olista01, rengolin Reviewed By: rengolin Subscribers: rengolin, javed.absar, kristof.beyls, rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D44467 llvm-svn: 327709
* [ARM] Fix a check in vmov/vmvn immediate parsingMikhail Maltsev2018-03-161-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: Currently the check is incorrect and the following invalid instruction is accepted and incorrectly assembled: vmov.i32 d2, #0x00a500a6 This patch fixes the issue. Reviewers: olista01, rengolin Reviewed By: rengolin Subscribers: SjoerdMeijer, javed.absar, rogfer01, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44460 llvm-svn: 327704
* [MC] Always emit relocations for same-section function referencesReid Kleckner2018-03-141-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We already emit relocations in this case when the "incremental linker compatible" flag is set, but it turns out these relocations are also required for /guard:cf. Now that we have two use cases for this behavior, let's make it unconditional to try to keep things simple. We never hit this problem in Clang because it always sets the "incremental linker compatible" flag when targeting MSVC. However, LLD LTO doesn't set this flag, so we'd get CFG failures at runtime when using ThinLTO and /guard:cf. We probably don't want LLD LTO to set the "incremental linker compatible" assembler flag, since this has nothing to do with incremental linking, and we don't need to timestamp LTO temporary objects. Fixes PR36624. Reviewers: inglorion, espindola, majnemer Subscribers: mehdi_amini, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D44485 llvm-svn: 327557
* [mips] Add support for CRC ASEPetar Jovanovic2018-03-1412-0/+206
| | | | | | | | | | | | | | | | | | | This includes Instructions: crc32b, crc32h, crc32w, crc32d, crc32cb, crc32ch, crc32cw, crc32cd Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc Attribute: crc .MIPS.abiflags: CRC (0x8000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44176 llvm-svn: 327511
* Revert "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-03-1315-574/+82
| | | | | | | | | This appears to have broken the expensive checks bot in a strange fashion. Reverting until I can investigate. This reverts r327409. llvm-svn: 327427
* [mips] Guard traps for microMIPS correctlySimon Dardis2018-03-1315-82/+574
| | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 llvm-svn: 327409
* [mips] Fix the definitions of the EVA instructionsSimon Dardis2018-03-1311-66/+180
| | | | | | | | | | Correct their availability to their respective ISAs. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D44209 llvm-svn: 327403
* [llvm] Fix mc testsAlexander Shaposhnikov2018-03-121-0/+4
| | | | | | | This diff adjusts the mc tests after changing the format of llvm-readobj output for .group sections. llvm-svn: 327349
* [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD InstructionDmitry Preobrazhensky2018-03-122-2/+31
| | | | | | | | | See bug 36558: https://bugs.llvm.org/show_bug.cgi?id=36558 Differential Revision: https://reviews.llvm.org/D43950 Reviewers: artem.tamazov, arsenm llvm-svn: 327299
* [AMDGPU][MC] Corrected GATHER4 opcodesDmitry Preobrazhensky2018-03-126-2901/+1087
| | | | | | | | | See bug 36252: https://bugs.llvm.org/show_bug.cgi?id=36252 Differential Revision: https://reviews.llvm.org/D43874 Reviewers: artem.tamazov, arsenm llvm-svn: 327278
* MC intel asm parser: Allow @ at the start of function names.Nico Weber2018-03-121-1/+4
| | | | | | | | Ports parts of r193000 to the intel parser. Fixes part of PR36676. https://reviews.llvm.org/D44359 llvm-svn: 327262
* Don't treat .symver as a regular alias definition.Rafael Espindola2018-03-091-3/+3
| | | | | | | | | | | | | | This patch starts simplifying the handling of .symver. For now it just moves the responsibility for creating an alias down to the streamer. With that the asm streamer can pass a .symver unchanged, which is nice since gas cannot parse "foo@bar = zed". In a followup I hope to move the handling down to the writer so that we don't need special hacks for avoiding breaking names with @@@ on windows. llvm-svn: 327101
* Revert "[DWARF] Fix mixing assembler -g with DWARF .file directives."Paul Robinson2018-03-091-1/+1
| | | | | | | This reverts commit d6d9ac1ab5039ba1fe0f63c36eac2bdd9f0a79c9. aka r327073 llvm-svn: 327083
* [DWARF] Fix mixing assembler -g with DWARF .file directives.Paul Robinson2018-03-081-1/+1
| | | | | | | | | | | We were effectively overriding an explicit '.file' directive with info for the assembler source. That shouldn't happen. Fixes PR36636. Differential Revision: https://reviews.llvm.org/D44265 llvm-svn: 327073
* Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""Alexander Kornienko2018-03-075-48/+12
| | | | | | | | | | | | | | | | This reverts commit r326839. r326839 breaks assembly file parsing: $ cat q.c void g() {} $ clang -S q.c -g $ clang -g -c q.s q.s:9:2: error: file number already allocated .file 1 "/tmp/test" "q.c" ^ llvm-svn: 326902
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