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* AMDGPU: Add D16 instructions preserve unused bits featureKonstantin Zhuravlyov2018-05-041-0/+1
| | | | | | | | | - Predicate D16 patterns on this new feature - Added this new feature to gfx900/2/4 Differential Revision: https://reviews.llvm.org/D46366 llvm-svn: 331551
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-049-4/+40
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* [WebAssembly] MC: Don't litter test directory.Benjamin Kramer2018-05-031-1/+1
| | | | llvm-svn: 331442
* [WebAssembly] MC: Create and use first class section symbolsSam Clegg2018-05-022-42/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D46335 llvm-svn: 331413
* [COFF, ARM64] Hook up a few remaining relocationsMartin Storsjo2018-05-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D46355 llvm-svn: 331384
* [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.Sander de Smalen2018-05-024-0/+136
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46270 llvm-svn: 331352
* [AArch64][SVE] Asm: Support for scatter ST1 store instructions.Sander de Smalen2018-05-028-0/+544
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46248 llvm-svn: 331349
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-029-40/+4
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-029-4/+40
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 ↵Sander de Smalen2018-05-0216-0/+812
| | | | | | | | | | | | load/store instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46269 llvm-svn: 331343
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-0216-11/+495
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector ↵Sander de Smalen2018-05-028-0/+476
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46250 llvm-svn: 331339
* AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago)Konstantin Zhuravlyov2018-05-011-1/+1
| | | | llvm-svn: 331298
* AMDGPU: Add missing gfx904 testsKonstantin Zhuravlyov2018-05-012-0/+2
| | | | llvm-svn: 331284
* [WebAssembly] llvm-readobj: display symbols names in relocationsSam Clegg2018-05-014-49/+53
| | | | | | Differential Revision: https://reviews.llvm.org/D46296 llvm-svn: 331279
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store ↵Sander de Smalen2018-05-018-0/+171
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46121 llvm-svn: 331260
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-016-0/+83
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-013-9/+9
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* [MC] Change AsmParser to leverage Assembler during evaluationNirav Dave2018-04-304-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | Teach AsmParser to check with Assembler for when evaluating constant expressions. This improves the handing of preprocessor expressions that must be resolved at parse time. This idiom can be found as assembling-time assertion checks in source-level assemblers. Note that this relies on the MCStreamer to keep sufficient tabs on Section / Fragment information which the MCAsmStreamer does not. As a result the textual output may fail where the equivalent object generation would pass. This can most easily be resolved by folding the MCAsmStreamer and MCObjectStreamer together which is planned for in a separate patch. Currently, this feature is only enabled for assembly input, keeping IR compilation consistent between assembly and object generation. Reviewers: echristo, rnk, probinson, espindola, peter.smith Reviewed By: peter.smith Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45164 llvm-svn: 331218
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-306-93/+1276
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-302-8/+8
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-3010-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the 'isSVEVectorRegWithShiftExtend' function to improve diagnostics for SVE's gather load (scalar + vector) addressing modes. Instead of always suggesting the 'unscaled' addressing mode, the use of DiagnosticPredicate enables a more specific error message in the context where the scaling is incorrect. For example: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] ^ shift amount should be '1' Instead of suggesting the packed, unscaled addressing mode: expected 'z[0..31].d, (uxtw|sxtw)' the assembler now suggests using the proper scaling: expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46124 llvm-svn: 331162
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-302-1/+4
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.Craig Topper2018-04-302-8/+0
| | | | | | I assume this was done because gas accepted it at one point, but current versions of gas don't. llvm-svn: 331154
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-291-0/+9
| | | | | | This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas. llvm-svn: 331149
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load ↵Sander de Smalen2018-04-2928-0/+864
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46120 llvm-svn: 331145
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-292-4/+22
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-292-23/+11
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [X86] Remove REX.W from 64-bit mode BND instructions.Craig Topper2018-04-281-6/+6
| | | | | | As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102
* [X86] Rename BNDMOV instructions and hide redundant instruction encoding ↵Craig Topper2018-04-281-1/+1
| | | | | | | | | | | | from the assembler. Favor the 0x1a encoding for register/register move to match gas. The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV. Hide the _REV encoding from the assembler but leave it for the disassembler. llvm-svn: 331101
* ELFObjectWriter: Allow one unique symver per symbolVlad Tsyrklevich2018-04-272-0/+12
| | | | | | | | | | | | | | | | | Summary: Only allow a single unique .symver alias per symbol. This matches the behavior of gas. I noticed that we ignored multiple mismatched symver directives looking at https://reviews.llvm.org/D45798 Reviewers: pcc, tejohnson, espindola Reviewed By: pcc Subscribers: emaste, arichardson, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D45845 llvm-svn: 331078
* [MC] Undo spurious commit added into r331052.Nirav Dave2018-04-274-81/+2
| | | | llvm-svn: 331055
* [MC] Provide default value for IsResolved.Nirav Dave2018-04-274-2/+81
| | | | llvm-svn: 331052
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-2715-0/+322
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [WebAssembly] Section symbols must have local bindingSam Clegg2018-04-271-1/+63
| | | | | | | | | | Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll. Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46160 llvm-svn: 331005
* Fix WAsm dwarfdump.ll test on WindowsReid Kleckner2018-04-261-3/+3
| | | | llvm-svn: 330995
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-267-24/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [WebAssembly] Write DWARF data into wasm object fileSam Clegg2018-04-262-3/+258
| | | | | | | | | | | - Writes ".debug_XXX" into corresponding custom sections. - Writes relocation records into "reloc.debug_XXX" sections. Patch by Yury Delendik! Differential Revision: https://reviews.llvm.org/D44184 llvm-svn: 330982
* Specify REQUIRES: default_triple in a few testsJustin Bogner2018-04-264-0/+4
| | | | | | These were all failing when specifying LLVM_DEFAULT_TARGET_TRIPLE=''. llvm-svn: 330977
* [WebAssembly] Add version to object file metadataSam Clegg2018-04-269-15/+11
| | | | | | | | | | Summary: See https://github.com/WebAssembly/tool-conventions/issues/54 Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46069 llvm-svn: 330969
* [mips] Fix a test case which is keeping the expensive checks bot win red (NFC)Simon Dardis2018-04-261-3/+0
| | | | llvm-svn: 330956
* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-262-10/+29
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
* [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.Sander de Smalen2018-04-2611-96/+96
| | | | | | | | | | | | | | | | | | | | This patch extends the PredicateMethod of AsmOperands used in SVE's LD1 instructions with a DiagnosticPredicate. This makes them 'context sensitive' to the operand that has been parsed and tells the user to use the right register (with expected shift/extend), rather than telling the immediate is out of range when it actually parsed a register. Patch [2/2] in a series to improve assembler diagnostics for SVE: - Patch [1/2]: https://reviews.llvm.org/D45879 - Patch [2/2]: https://reviews.llvm.org/D45880 Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45880 llvm-svn: 330934
* [AArch64][SVE] Asm: Negative tests for all LD1 gather (scalar+vector) load ↵Sander de Smalen2018-04-2614-0/+541
| | | | | | | | | | | | | | | | | | instructions. Patch [3/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45958 llvm-svn: 330929
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load ↵Sander de Smalen2018-04-2618-16/+640
| | | | | | | | | | | | | | | | | | instructions. Patch [2/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46023 llvm-svn: 330928
* [codeview] Ignore .cv_loc directives at the end of a functionReid Kleckner2018-04-251-0/+183
| | | | | | | | | | If no data or instructions are emitted after a location directive, we should clear the cv_loc when we change sections, or it will be emitted at the beginning of the next section. This violates our invariant that all .cv_loc directives belong to the same section. Add clearer assertions for this. llvm-svn: 330884
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ↵Alex Bradbury2018-04-251-0/+20
| | | | | | | | | | coincides with a register name Previously `call zero`, `call f0` etc would fail. This leads to compilation failures if building programs that define functions with those names and using -save-temps. llvm-svn: 330846
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-252-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To do this: 1. Add PseudoCALLIndirct to match indirect function call. 2. Add PseudoCALL to support parsing and print pseudo `call` in assembly 3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type while encoding: auipc ra, func jalr ra, ra, 0 If we expand PseudoCALL before emitting assembly, we will see auipc and jalr pair when compile with -S. It's hard for assembly parser to parsing this pair and identify it's semantic is function call and then insert R_RISCV_CALL relocation type. Although we could insert R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL. Due to RISCV relocation design, auipc and jalr pair only can relax to jal with R_RISCV_CALL + R_RISCV_RELAX relocation types. We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before emitting assembly(RISCVAsmPrinter) because we want to preserve call pseudoinstruction in assembly code. It's more readable and assembly parser could identify call assembly and insert R_RISCV_CALL relocation type. Differential Revision: https://reviews.llvm.org/D45859 llvm-svn: 330826
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-2510-7/+42
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* Reland "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-04-2412-216/+216
| | | | | | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
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