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* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-263-0/+30
| | | | llvm-svn: 222849
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-263-0/+51
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [Hexagon] Adding and64, or64, and xor64 instructions.Colin LeMahieu2014-11-263-0/+30
| | | | llvm-svn: 222846
* Update AArch64 ELF relocations to ABI 1.0Will Newton2014-11-265-5/+5
| | | | | | | | | | | | | | | | | | | | This mostly entails adding relocations, however there are a couple of changes to existing relocations: 1. R_AARCH64_NONE is defined to be zero rather than 256 R_AARCH64_NONE has been defined to be zero for a long time elsewhere e.g. binutils and glibc since the submission of the AArch64 port in 2012 so this is required for compatibility. 2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21 I don't think there is any way for relocation names to leak out of LLVM so this should not break anything. Tested with check-all with no regressions. llvm-svn: 222821
* [Hexagon] Adding add64 and sub64 instructions.Colin LeMahieu2014-11-252-0/+20
| | | | llvm-svn: 222795
* Reverting 222792Colin LeMahieu2014-11-253-30/+0
| | | | llvm-svn: 222793
* [Hexagon] Adding compare with immediate instructions.Colin LeMahieu2014-11-253-0/+30
| | | | llvm-svn: 222792
* [Hexagon] [NFC] Adding trailing whitespace to test files.Colin LeMahieu2014-11-2517-17/+17
| | | | llvm-svn: 222785
* [Hexagon] Adding C2_mux instruction.Colin LeMahieu2014-11-251-0/+10
| | | | llvm-svn: 222784
* [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.Colin LeMahieu2014-11-255-0/+50
| | | | llvm-svn: 222771
* Reapply 222538 and update tests to explicitly request small code modelJoerg Sonnenberger2014-11-2520-20/+60
| | | | | | | | | | | | | | | and PIC: Allow FDE references outside the +/-2GB range supported by PC relative offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise. Patch from Akos Kiss. Differential Revision: http://reviews.llvm.org/D6079 llvm-svn: 222760
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-252-0/+10
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignmentUlrich Weigand2014-11-241-0/+19
| | | | | | | | | | | When processing an assignment in the integrated assembler that sets a symbol to the value of another symbol, we need to copy the st_other bits that encode the local entry point offset. Modeled after MipsTargetELFStreamer::emitAssignment handling of the ELF::STO_MIPS_MICROMIPS flag. llvm-svn: 222672
* [Hexagon] Adding asrh instruction, removing unused multiclasses.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222670
* [Hexagon] Adding aslh instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222668
* [Hexagon] Adding zxth instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222662
* [Hexagon] Adding zxtb instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222660
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-241-4/+2
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-242-0/+45
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-242-0/+90
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2014-11-211-2/+8
| | | | | | arguments. llvm-svn: 222587
* [Hexagon] Adding sxth instruction.Colin LeMahieu2014-11-211-0/+10
| | | | llvm-svn: 222577
* [Hexagon] Adding sxtb instruction. Renaming some identically named classes ↵Colin LeMahieu2014-11-211-0/+10
| | | | | | that will be removed after converting referencing defs. llvm-svn: 222575
* [ELF] Prevent ARM ELF object writer from generating deprecated relocation ↵Jyoti Allur2014-11-201-2/+2
| | | | | | code R_ARM_PLT32 llvm-svn: 222414
* [Hexagon] Adding A2_xor instruction with IR selection pattern and test.Colin LeMahieu2014-11-191-0/+10
| | | | llvm-svn: 222399
* [Hexagon] Adding A2_or instruction with IR selection pattern and test.Colin LeMahieu2014-11-191-0/+10
| | | | llvm-svn: 222396
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-194-24/+67
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek2014-11-191-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D6169 llvm-svn: 222355
* [mips][microMIPS] Add disassembler tests for new microMIPS 32-bitJozef Kolek2014-11-192-0/+42
| | | | | | | | instructions: LWXS, BGEZALS, BLTZALS, BEQZC, BNEZC, JALS and JALRS. http://reviews.llvm.org/D5413 llvm-svn: 222349
* [mips][microMIPS] Implement LWXS instruction.Jozef Kolek2014-11-191-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D5407 llvm-svn: 222348
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* [Hexagon] Adding A2_and instruction.Colin LeMahieu2014-11-181-0/+10
| | | | llvm-svn: 222274
* [Hexagon] Adding A2_sub instructionColin LeMahieu2014-11-182-0/+10
| | | | | | Renaming test files. llvm-svn: 222263
* [Hexagon] Converting from ADD_rr to A2_add which has encoding bits.Colin LeMahieu2014-11-181-0/+10
| | | | | | Adding test to show correct instruction selection and encoding. llvm-svn: 222249
* R600/SI: Start implementing an assemblerTom Stellard2014-11-142-0/+54
| | | | | | | This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
* [mips] Add hardware register name "hwr_ulr" ($29)Vasileios Kalintiris2014-11-111-0/+7
| | | | | | | | | | The canonical name when printing assembly is still $29. The reason is that GAS does not accept "$hwr_ulr" at the moment. This addresses the comments from r221307, which reverted the original commit r221299. llvm-svn: 221685
* Recommit "[mips] Add names and tests for the hardware registers"Vasileios Kalintiris2014-11-115-2/+216
| | | | | | | The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
* llvm-objdump: Skip empty sections when dumping contentsDavid Majnemer2014-11-112-13/+2
| | | | | | | Empty sections are just noise when using objdump. This is similar to what binutils does. llvm-svn: 221680
* MC, COFF: Use relocations for function references inside the sectionDavid Majnemer2014-11-111-3/+4
| | | | | | | | | | | | | | | | | | Referencing one symbol from another in the same section does not generally require a relocation. However, the MS linker has a feature called /INCREMENTAL which enables incremental links. It achieves this by creating thunks to the actual function and redirecting all relocations to point to the thunk. This breaks down with the old scheme if you have a function which references, say, itself. On x86_64, we would use %rip relative addressing to reference the start of the function from out current position. This would lead to miscompiles because other references might reference the thunk instead, breaking function pointer equality. This fixes PR21520. llvm-svn: 221678
* [Hexagon] Adding basic Hexagon ELF object emitter.Colin LeMahieu2014-11-062-0/+10
| | | | llvm-svn: 221465
* [mips] Improve error/warning messages and testing for the .cpload assembler ↵Toma Tabacu2014-11-062-17/+38
| | | | | | | | | | | | | | | | | | directive. Summary: Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled. Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5465 llvm-svn: 221447
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-052-0/+5
| | | | llvm-svn: 221367
* [mips][microMIPS] Mark symbols as microMIPS if necessaryZoran Jovanovic2014-11-052-0/+89
| | | | | | Differential Revision: http://reviews.llvm.org/D6039 llvm-svn: 221355
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-052-5/+0
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-052-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* Fix bashism in tests added by r221341Oliver Stannard2014-11-052-4/+4
| | | | llvm-svn: 221342
* [ARM] Honor FeatureD16 in the assembler and disassemblerOliver Stannard2014-11-054-7/+54
| | | | | | | | | | | | | | | Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-047-225/+4
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* Don't produce relocations for a difference in a section with no symbols.Rafael Espindola2014-11-042-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were producing a relocation for ---------------- .section foo,bar La: Lb: .long La-Lb -------------- but not for --------------------- .section foo,bar zed: La: Lb: .long La-Lb ---------------- This patch handles the case where both fragments are part of the first atom in a section and there is no corresponding symbol to that atom. This fixes pr21328. llvm-svn: 221304
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-047-4/+225
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
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