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* [WebAssembly] Support weak defined symbolsSam Clegg2017-07-071-5/+27
| | | | | | | | | | | | Model weakly defined symbols as symbols that are both exports and imported and marked as weak. Local references to the symbols refer to the import but the linker can resolve this to the weak export if not strong symbol is found at link time. Differential Revision: https://reviews.llvm.org/D35029 llvm-svn: 307348
* Use @LINE in two more tests.Rafael Espindola2017-07-062-4/+2
| | | | llvm-svn: 307318
* Add @LINE to checks in a test.Rafael Espindola2017-07-061-22/+29
| | | | | | This makes it a lot easier to see which error failed a check. llvm-svn: 307300
* [WebAssembly] Fix types for address taken functionsSam Clegg2017-07-051-20/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D34966 llvm-svn: 307198
* [WebAssembly] MC: Don't generate extra types for weak aliasSam Clegg2017-07-051-1/+8
| | | | | | | | | | Previously we were generating a void(void) function type for a weak alias. Update the weak-alias test case to catch this. Differential Revision: https://reviews.llvm.org/D34734 llvm-svn: 307194
* Add a test for relocation addend on mips.Rafael Espindola2017-07-051-0/+21
| | | | | | | An lld test found a bug in a llvm patch I am working on. It is better to have test coverage for that in llvm too. llvm-svn: 307192
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-0/+68
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* [AVR] Remove a bunch of now-obselete testsDylan McKay2017-07-014-20/+0
| | | | | | The fixups in these instructions are now lowered into relocations. llvm-svn: 306947
* Fix ODR violations due to abuse of LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTORRichard Smith2017-06-302-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This is a short-term fix for PR33650 aimed to get the modules build bots green again. Remove all the places where we use the LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTOR macros to try to locally specialize a global template for a global type. That's not how C++ works. Instead, we now centrally define how to format vectors of fundamental types and of string (std::string and StringRef). We use flow formatting for the former cases, since that's the obvious right thing to do; in the latter case, it's less clear what the right choice is, but flow formatting is really bad for some cases (due to very long strings), so we pick block formatting. (Many of the cases that were using flow formatting for strings are improved by this change.) Other than the flow -> block formatting change for some vectors of strings, this should result in no functionality change. Differential Revision: https://reviews.llvm.org/D34907 Corresponding updates to clang, clang-tools-extra, and lld to follow. llvm-svn: 306878
* [SystemZ] Add all remaining instructionsUlrich Weigand2017-06-309-3/+4172
| | | | | | | | | | | This adds all remaining instructions that were still missing, mostly privileged and semi-privileged system-level instructions. These are provided for use with the assembler and disassembler only. This brings the LLVM assembler / disassembler to parity with the GNU binutils tools. llvm-svn: 306876
* [MIPS] Handle PIC load address macro instructions in N64.Simon Dardis2017-06-302-0/+71
| | | | | | | | | | | | | | | | | | | | In particular, use CALL16 (similar to O32) for address loads into T9 for certain cases. Otherwise use a %got_disp relocation to load the address of a symbol. Small offsets (small enough to fit in a 16-bit signed immediate) can be used and are added to the symbol address after it is loaded from the GOT. Larger offsets are currently unsupported and result in an error from the assembler. Reviewers: sdardis Reviewed By: sdardis Patch by: John Baldwin Subscribers: llvm-commits, seanbruno, arichardson, emaste, dim Differential Revision: https://reviews.llvm.org/D33948 llvm-svn: 306831
* [SystemZ] Add missing high-word facility instructionsUlrich Weigand2017-06-304-0/+454
| | | | | | | | | | | There are a few instructions provided by the high-word facility (z196) that we cannot easily exploit for code generation. This patch at least adds those missing instructions for the assembler and disassembler. This means that now all nonprivileged instructions up to z13 are supported by the LLVM assembler / disassembler. llvm-svn: 306821
* Fix PR33625.Rafael Espindola2017-06-281-0/+12
| | | | | | We were failing to convert this expression to pcrel. llvm-svn: 306573
* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-271-0/+8
| | | | | | | | | | | | | | | | Summary: This is the llvm part of the initial implementation to support Windows ARM64 COFF format. I will gradually add more functionality in subsequent patches. Reviewers: ruiu, rnk, t.p.northover, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34705 llvm-svn: 306490
* [WebAssembly] Add data size and alignement to linking sectionSam Clegg2017-06-273-44/+54
| | | | | | | | | The overal size of the data section (including BSS) is otherwise not included in the wasm binary. Differential Revision: https://reviews.llvm.org/D34657 llvm-svn: 306459
* [X86][AsmParser][MS-compatability] Binary/Unary operators enhancementsCoby Tayree2017-06-271-0/+17
| | | | | | | | | | | Introducing MOD binary operator https://msdn.microsoft.com/en-us/library/hha180wt.aspx Enhancing unary operators NEG and NOT, to support more complex patterns Differential Revision: https://reviews.llvm.org/D33876 llvm-svn: 306425
* [mips] Add instruction aliases for ds(r|l)l.Simon Dardis2017-06-279-3/+39
| | | | | | | Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
* [WebAssembly] Add more support for weak symbolsSam Clegg2017-06-262-0/+67
| | | | | | | | | Add weak symbol tests to MC Add symbol flags to output of `llvm-readobj -t`. Differential Revision: https://reviews.llvm.org/D34635 llvm-svn: 306330
* fix trivial typo in comment, NFCHiroshi Inoue2017-06-261-1/+1
| | | | llvm-svn: 306274
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-9/+27
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* Reland r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-236-9/+9
| | | | | | | | | | | | | | | | After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
* Revert r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-236-9/+9
| | | | | | | | | | | | | | | ELF/mips-plt-r6.s in lld-test is failing. Reverting the change. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306099
* [mips] Fix register positions in the aui/daui instructionsPetar Jovanovic2017-06-236-9/+9
| | | | | | | | | | | | Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D33988 llvm-svn: 306095
* COFF: Produce an error on invalid pcrel relocs.Rafael Espindola2017-06-232-25/+18
| | | | | | | | | | X86_64 COFF only has support for 32 bit pcrel relocations. Produce an error on all others. Note that gnu as has extended the relocation values to support this. It is not clear if we should support the gnu extension. llvm-svn: 306082
* Make the test a bit more strict. NFC.Rafael Espindola2017-06-231-62/+64
| | | | llvm-svn: 306080
* COFF: handle "undef - ." expressions.Rafael Espindola2017-06-232-6/+10
| | | | | | | This is another thing that the ELF implementation can do but is missing from COFF. llvm-svn: 306078
* Change creation of relative relocations on COFF.Rafael Espindola2017-06-222-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For whatever reason, when processing .globl foo foo: .data bar: .long foo-bar llvm-mc creates a relocation with the section: 0x0 IMAGE_REL_I386_REL32 .text This is different than when the relocation is relative from the beginning. For example, a file with call foo produces 0x0 IMAGE_REL_I386_REL32 foo I would like to refactor the logic for converting "foo - ." into a relative relocation so that it is shared with ELF. This is the first step and just changes the coff implementation to match what ELF (and COFF in the case of calls) does. llvm-svn: 306063
* [MC] Allow assembling .secidx and .secrel32 for undefined symbolsReid Kleckner2017-06-222-10/+30
| | | | | | | | | | | There's nothing incorrect about emitting such relocations against symbols defined in other objects. The code in EmitCOFFSec* was missing the visitUsedExpr part of MCStreamer::EmitValueImpl, so these symbols were not being registered with the object file assembler. This will be used to make reduced test cases for LLD. llvm-svn: 306057
* Add a common error checking for some invalid expressions.Rafael Espindola2017-06-223-4/+8
| | | | | | | This refactors a bit of duplicated code and fixes an assertion failure on ELF. llvm-svn: 306035
* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-222-0/+58
| | | | | | | | | | | | | | | Intrinsic already existed for llvm.SI.tbuffer.store Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.* Added CodeGen tests for the 2 new variants added. Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr Differential Revision: https://reviews.llvm.org/D30687 llvm-svn: 306031
* [Hexagon] Handle a global operand to A2_addi when creating duplexesKrzysztof Parzyszek2017-06-221-0/+15
| | | | llvm-svn: 306012
* [ARM] Create relocations for beq.w branches to ARM function syms.Florian Hahn2017-06-221-0/+39
| | | | | | | | | | | | | | | | | | Summary: The ARM ELF ABI requires the linker to do interworking for wide conditional branches from Thumb code to ARM code. That was pointed out by @peter.smith in the comments for D33436. Reviewers: rafael, peter.smith, echristo Reviewed By: peter.smith Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith Differential Revision: https://reviews.llvm.org/D34447 llvm-svn: 306009
* [mips] Allow $AT to be used as a register namePetar Jovanovic2017-06-223-0/+3
| | | | | | | | | | | This patch allows $AT to be used as a register name in assembly files. Currently only $at is recognized as a valid register name. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34348 llvm-svn: 306007
* [mips] Implement the ".rdata" MIPS assembly directive.Simon Dardis2017-06-221-0/+13
| | | | | | | | | | | | | | Rather than creating a separate ".rdata" section distinct from the customary ".rodata" in ELF, ".rdata" switches to the ".rodata" section. This patch relands r305949 and r305950 with the correct commit message and addresses nit raised during review. Patch By: John Baldwin! Differential Revision: https://reviews.llvm.org/D34452 llvm-svn: 305995
* [ARM] Add .w aliases of MOV with shifted operandJohn Brawn2017-06-221-0/+16
| | | | | | | | These appear to have been simply missing. Differential Revision: https://reviews.llvm.org/D34461 llvm-svn: 305993
* Also test thumb.Rafael Espindola2017-06-221-1/+11
| | | | llvm-svn: 305976
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-0/+1752
| | | | | | | | | | See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509 Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin Differential Revision: https://reviews.llvm.org/D34360 llvm-svn: 305923
* [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is ↵Dmitry Preobrazhensky2017-06-213-9/+33
| | | | | | | | | | | | different than any of the src See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D34003 llvm-svn: 305915
* Simplify test.Rafael Espindola2017-06-211-40/+8
| | | | llvm-svn: 305881
* Make this test a bit more strict. NFC.Rafael Espindola2017-06-201-4/+3
| | | | llvm-svn: 305855
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-201-0/+87
| | | | llvm-svn: 305838
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.Artem Tamazov2017-06-195-82692/+259228
| | | | | | | | | | | A new Gfx9 dasm test added with approx 29000 cases. Existing tests extended by (approx.): * Gfx7 asm: 5000 test cases * Gfx8 asm: 5000 test cases * Gfx9 asm: 14400 test cases * Gfx8 dasm: 5200 test cases llvm-svn: 305702
* [WebAssembly] Use __stack_pointer global when writing wasm binarySam Clegg2017-06-162-3/+23
| | | | | | | | | | | | | | | | | | This ensures that symbolic relocations are generated for stack pointer manipulations. These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB. This change also adds support for reading relocations of this type in WasmObjectFile.cpp. Since its a globally imported symbol this does mean that the get_global/set_global instruction won't be valid until the objects are linked that global used in no longer an imported global. Differential Revision: https://reviews.llvm.org/D34172 llvm-svn: 305616
* MC, Object: Reserve a section type, SHT_LLVM_ODRTAB, for the ODR table.Peter Collingbourne2017-06-141-0/+12
| | | | | | | | | | | | | | This is part of the ODR checker proposal: http://lists.llvm.org/pipermail/llvm-dev/2017-June/113820.html Per discussion on the gnu-gabi mailing list [1] the section type range 0x6fff4c00..0x6fff4cff is reserved for LLVM. [1] https://sourceware.org/ml/gnu-gabi/2017-q2/msg00030.html Differential Revision: https://reviews.llvm.org/D33978 llvm-svn: 305407
* [WebAssembly] Fix symbol type for addresses of external functionsSam Clegg2017-06-132-2/+27
| | | | | | | | | | | | | | These symbols were previously not being marked as functions so were appearing as globals instead, and with the incorrect relocation type. Without this fix, objects that take address of external functions include them as global imports rather than function imports which then fails at link time. Differential Revision: https://reviews.llvm.org/D34068 llvm-svn: 305263
* [WebAssembly] MC: Fix value of R_WEBASSEMBLY_TABLE_INDEX relocationsSam Clegg2017-06-121-0/+48
| | | | | | | | | | | | | Previously we were writing the value function index space value but for these types of relocations we want to be writing the table element index space value. Add a test case for these relocation types that fails without this change. Differential Revision: https://reviews.llvm.org/D33962 llvm-svn: 305253
* IR: Replace the "Linker Options" module flag with "llvm.linker.options" ↵Peter Collingbourne2017-06-123-11/+10
| | | | | | | | | | named metadata. The new metadata is easier to manipulate than module flags. Differential Revision: https://reviews.llvm.org/D31349 llvm-svn: 305227
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-123-0/+37
| | | | | | | | | | | Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction. Commit on behalf of STEFAN PINTILIE. Differential Revision: https://reviews.llvm.org/D33940 llvm-svn: 305210
* AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault2017-06-122-1/+42
| | | | llvm-svn: 305194
* AMDGPU : Fix ISA Version Definitions.Wei Ding2017-06-101-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D28531 llvm-svn: 305137
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