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* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-034-0/+99
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-034-99/+0
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-034-0/+99
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [AArch64] ILP32 Backend Relocation SupportJoel Jones2017-05-0212-139/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and TLSDESC_ADD_LO12 relocations Rearrange ordering in AArch64.def to follow relocation encoding Fix name: R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC Add support for several "TLS", "TLSGD", and "TLSLD" relocations for ILP32 Fix return values from isNonILP32reloc Add implementations for R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC, R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC, *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC, *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC Modify error messages to give name of equivalent relocation in the ABI not being used, along with better checking for non-existent requested relocations. Added assembler support for "pg_hi21_nc" Relocation definitions added without implementations: R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21, R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21, R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19, R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL, R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL, R_AARCH64_P32_TLSDESC Fix encoding: R_AARCH64_P32_TLSDESC_ADR_PAGE21 Reviewers: Peter Smith Patch by: Joel Jones (jjones@cavium.com) Differential Revision: https://reviews.llvm.org/D32072 llvm-svn: 301980
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-021-0/+13
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* [Hexagon] Make sure duplexed dealloc_returns are checked for double jumpsKrzysztof Parzyszek2017-05-021-0/+7
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301951
* [Hexagon] Move checking AXOK to checkerKrzysztof Parzyszek2017-05-022-0/+13
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301949
* [Hexagon] Extract function that checks endloops with other branchesKrzysztof Parzyszek2017-05-022-19/+12
| | | | | | | | Change location number to point to conflicting branch instruction. Patch by Colin LeMahieu. llvm-svn: 301946
* Revert "Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and"Zachary Turner2017-05-0216-624/+139
| | | | | | | | This reverts commit c08155afc5d3230792da2ad30a046a8617735a73. This is causing undefined symbol errors with some of the constants. llvm-svn: 301944
* Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 andJoel Jones2017-05-0216-139/+624
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLSDESC_ADD_LO12 relocations Rearrange ordering in AArch64.def to follow relocation encoding Fix name: R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC Add support for several "TLS", "TLSGD", and "TLSLD" relocations for ILP32 Fix return values from isNonILP32reloc Add implementations for R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC, R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC, *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC, *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC Modify error messages to give name of equivalent relocation in the ABI not being used, along with better checking for non-existent requested relocations. Added assembler support for "pg_hi21_nc" Relocation definitions added without implementations: R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21, R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21, R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19, R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL, R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL, R_AARCH64_P32_TLSDESC Fix encoding: R_AARCH64_P32_TLSDESC_ADR_PAGE21 Reviewers: Peter Smith Patch by: Joel Jones (jjones@cavium.com) Differential Revision: https://reviews.llvm.org/D32072 llvm-svn: 301939
* Add llvm::object::getELFSectionTypeName().Rafael Espindola2017-05-021-1/+1
| | | | | | | | | | | This is motivated by https://reviews.llvm.org/D32488 where I am trying to add printing of the section type for incompatible sections to LLD error messages. This patch allows us to use the same code in llvm-readobj and LLD instead of duplicating the function inside LLD. Patch by Alexander Richardson! llvm-svn: 301921
* [AArch64] armv8-A doesn't have LSE.Ahmed Bougacha2017-05-021-0/+8
| | | | | | | | | | | r288279 mistakenly added it to all arches, but it's only available from v8.1 onwards. The testcase is awkward, because (I suspect) of PR32873. Spotted by inspection. llvm-svn: 301890
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-014-0/+25
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-0/+15
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* Fix test for altmacroMichael Zuckerman2017-05-012-2/+2
| | | | llvm-svn: 301799
* [LLVM][inline-asm] Altmacro absolute expression '%' featureMichael Zuckerman2017-05-012-0/+99
| | | | | | | | | | | | | | | | | | | | | In this patch, I introduce a new alt macro feature. This feature adds meaning for the % when using it as a prefix to the calling macro arguments. In the altmacro mode, the percent sign '%' before an absolute expression convert the expression first to a string. As described in the https://sourceware.org/binutils/docs-2.27/as/Altmacro.html "Expression results as strings You can write `%expr' to evaluate the expression expr and use the result as a string." expression assumptions: 1. '%' can only evaluate an absolute expression. 2. Altmacro '%' must be the first character of the evaluated expression. 3. If no '%' is located before the expression, a regular module operation is expected. 4. The result of Absolute Expressions can be only integer. Differential Revision: https://reviews.llvm.org/D32526 llvm-svn: 301797
* [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offsetDylan McKay2017-04-302-4/+4
| | | | | | | Before this, the LDS/STS instructions would have their opcodes overwritten while linking. llvm-svn: 301782
* [mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of ↵Simon Atanasyan2017-04-301-1/+7
| | | | | | | | | | | microMIPS In case of microMIPS mode %gottprel operator should emit microMIPS relocation R_MICROMIPS_TLS_GOTTPREL, not R_MIPS_TLS_GOTTPREL. Differential Revision: http://reviews.llvm.org/D32617 llvm-svn: 301763
* [WebAssembly] Add size of section header to data relocation offsets.Sam Clegg2017-04-281-0/+26
| | | | | | | | | | | Also, add test for data relocations and fix addend to be signed. Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D32513 llvm-svn: 301690
* [WebAssembly] Write initial memory in pages not bytesSam Clegg2017-04-281-0/+5
| | | | | | | | Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D32660 llvm-svn: 301687
* [WebAssembly] Add some tests for wasm MC layerSam Clegg2017-04-282-0/+116
| | | | | | | | Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D32558 llvm-svn: 301606
* [AMDGPU] DPP: add support for GFX9Sam Kolton2017-04-272-138/+147
| | | | | | | | | | Reviewers: artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D32588 llvm-svn: 301551
* 2 tests that were lost in rL301390Andrew V. Tischenko2017-04-271-0/+7
| | | | llvm-svn: 301529
* [AMDGPU][MC] Added arg checks for vmcnt, expcnt, lgkmcnt helpersDmitry Preobrazhensky2017-04-262-0/+56
| | | | | | | | | | | | | | Summary of changes: - corrected vmcnt, expcnt, lgkmcnt helpers to checks their argument for truncation; - added saturated versions of these helpers. See bug 32711 for details: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32546 llvm-svn: 301439
* [AMDGPU][MC] Added check for truncation of SOPK imm operandDmitry Preobrazhensky2017-04-262-0/+27
| | | | | | | | | | See bug 30827: https://bugs.llvm.org//show_bug.cgi?id=30827 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32535 llvm-svn: 301418
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-262-14/+10
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9.Artem Tamazov2017-04-244-58050/+128900
| | | | llvm-svn: 301247
* [Arch64AsmParser] better diagnostic for isbSjoerd Meijer2017-04-241-0/+12
| | | | | | | | | | | Instruction isb takes as an operand either 'sy' or an immediate value. This improves the diagnostic when the string is not 'sy' and adds a test case for this which was missing. This also adds tests to check invalid inputs for dsb and dmb. Differential Revision: https://reviews.llvm.org/D32227 llvm-svn: 301165
* [ARM] Fix handling of mapping symbols when changing sectionsJohn Brawn2017-04-201-1/+18
| | | | | | | | | | | ChangeSection incorrectly registers LastEMSInfo as belonging to the previous section, not the current section. This happens to work when changing sections using .section, as the previous section is set to the current section before the call to ChangeSection, but not when using .popsection. Differential Revision: https://reviews.llvm.org/D32225 llvm-svn: 300831
* [AArch64] Fix handling of zero immediate in fmov instructionsJohn Brawn2017-04-201-5/+5
| | | | | | | | | | | Currently fmov #0 with a vector destination is handle incorrectly and results in fmov #-1.9375 being emitted but should instead give an error. This is due to the way we cope with fmov #0 with a scalar destination being an alias of fmov zr, so fix this by actually doing it through an alias. Differential Revision: https://reviews.llvm.org/D31949 llvm-svn: 300830
* [AArch64] Fix handling of integer fp immediatesJohn Brawn2017-04-201-0/+14
| | | | | | | | When an integer is used as an fp immediate we're failing to check the return value of getFP64Imm, so invalid values are silently permitted. Fix this by merging together the integer and real handling. llvm-svn: 300828
* [AMDGPU][mc][tests][NFC] Update bulk ISA tests for Gfx7 and Gfx8Artem Tamazov2017-04-192-4377/+10806
| | | | | | Added approx. 1100 gfx7 and 1040 gfx8 test cases. llvm-svn: 300734
* [ARM] Add hardware build attributes in assemblerOliver Stannard2017-04-181-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the assembler, we should emit build attributes based on the target selected with command-line options. This matches the GNU assembler's behaviour. We only do this for build attributes which describe the hardware that is expected to be available, not the ones that describe ABI compatibility. This is done by moving some of the attribute emission code to ARMTargetStreamer, so that it can be shared between the assembly and code-generation code paths. Since the assembler only creates a MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to check raw features, and not use the convenience functions in ARMSubtarget. If different attributes are later specified using the .eabi_attribute directive, then they will take precedence, as happens when the same .eabi_attribute is specified twice. This must be enabled by an option, because we don't want to do this when parsing inline assembly. The attributes would match the ones emitted at the start of the file, so wouldn't actually change the emitted object file, but the extra directives would be added to every inline assembly block when emitting assembly, which we'd like to avoid. The majority of the changes in the build-attributes.ll test are just re-ordering the directives, because the hardware attributes are now emitted before the ABI ones. However, I did fix one bug which I spotted: Tag_CPU_arch_profile was not being emitted for v6M. Differential revision: https://reviews.llvm.org/D31812 llvm-svn: 300547
* [AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.Dmitry Preobrazhensky2017-04-141-6/+6
| | | | | | | | | | Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31809 llvm-svn: 300319
* [AMDGPU][MC] Enabled constants for src operands of s_cbranch_g_forkDmitry Preobrazhensky2017-04-142-0/+15
| | | | | | | | | | Fixed bug 32619: https://bugs.llvm.org//show_bug.cgi?id=32619 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D31973 llvm-svn: 300318
* [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)Dmitry Preobrazhensky2017-04-123-1/+23
| | | | | | | | | | | | | | | | | | | | | | Added support for VI: - s_endpgm_saved - s_wakeup - s_rfe_restore_b64 - v_perm_b32 Enabled for VI: - v_mov_fed_b32 - v_mov_fed_b32_e64 See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D31931 llvm-svn: 300076
* [AMDGPU][MC] Corrected parsing of v_cmp_class* and v_cmpx_class*Dmitry Preobrazhensky2017-04-121-0/+24
| | | | | | | | | | Fixed bug 32565: https://bugs.llvm.org//show_bug.cgi?id=32565 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31820 llvm-svn: 300073
* [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CIDmitry Preobrazhensky2017-04-121-1/+1
| | | | | | | | | | | | Corrected encoding of V_MQSAD_U32_U8 for CI See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31810 llvm-svn: 300070
* [AMDGPU][MC] Corrected ds_wrxchg2* to support two offsetsDmitry Preobrazhensky2017-04-121-0/+16
| | | | | | | | | | Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31808 llvm-svn: 300066
* [AMDGPU][MC] Corrected src0 size for s_cbranch_joinDmitry Preobrazhensky2017-04-122-4/+12
| | | | | | | | | | Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159 Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31595 llvm-svn: 300055
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+19
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* [AsmParser]Emit an error if a macro has two (or more) parameters sharing the ↵Coby Tayree2017-04-081-0/+7
| | | | | | | | | | | | | same name Introducing a new error to macro parameters' parsing: currently, llvm-mc won't complain if a macro have two (or more) named params with the same name. this behavior is false, as there's no merit in having some params sharing a name. now, instead of tolerate such a phenomena - emit an appropriate error. Differential Revision: https://reviews.llvm.org/D31674 llvm-svn: 299815
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-075-39/+161
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [AMDGPU][MC] Fix for Bug 28158 + LIT testsDmitry Preobrazhensky2017-04-051-0/+15
| | | | | | | | | | | | | | | Added support of the following instructions: - s_cbranch_cdbgsys - s_cbranch_cdbgsys_and_user - s_cbranch_cdbgsys_or_user - s_cbranch_cdbguser - s_setkill Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31469 llvm-svn: 299567
* [AMDGPU][MC] Fix for Bug 28167 + LIT testsDmitry Preobrazhensky2017-04-051-0/+8
| | | | | | | | | | | | Corrected src0 for v_writelane_b32: - Enabled inline constants and literals for SI/CI (VOP2) - Enabled inline constants for VI (VOP3) Reviewers: vpykhtin, arsenm https://reviews.llvm.org/D31463 llvm-svn: 299555
* [AArch64] Crypto requires FP.James Molloy2017-04-051-0/+8
| | | | | | So if FP is disabled, crypto should also be disabled. llvm-svn: 299531
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-1/+1
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* [MC] Set defaults based on section names and support name suffixesPetr Hosek2017-04-041-0/+47
| | | | | | | | | | | | | Set correct default flags and section type based on its name for .text, .data, .bss, .init_array, .fini_array, .preinit_array, .tdata, and .tbss and support section name suffixes for .data.*, .rodata.*, .text.*, .bss.*, .tdata.* and .tbss.* which matches the behavior of GAS. Fixes PR31888. Differential Revision: https://reviews.llvm.org/D30229 llvm-svn: 299484
* Change section flag character for SHF_LINK_ORDER to "o".Evgeniy Stepanov2017-04-045-10/+10
| | | | | | | | GAS uses "m" as a compatibility alias for "M" (SHF_MERGE). "o" is free, except on ia64, where it already means SHF_LINK_ORDER. llvm-svn: 299479
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